From: "Chao Liu" <lc00631@tecorigin.com>

Hi, all:

Thanks to Alistair for the review~

PATCH v4:

Rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next

PATCH v3:

Use cpu_by_arch_id() instead of qemu_get_cpu(), when registering gpio in
sifive_plic_create().

PATCH v2:

During plic initialization, CPUSate is obtained by traversing qemu_get_cpu(),
which was an early design flaw (see PATCH v1 reviewed).

A better approach is to use riscv's hartid for indexing via the cpu_by_arch_id()
interface.

PATCH v1 (Reviewed):
https://lore.kernel.org/qemu-riscv/416e68f4-bf12-4218-ae2d-0246cc8ea8ec@linaro.org/T/#u

--
Regards,
Chao

Chao Liu (1):
  hw/riscv: fix PLIC hart topology configuration string when not getting
    CPUState correctly

 hw/intc/sifive_plic.c      | 4 ++--
 hw/riscv/boot.c            | 4 ++--
 hw/riscv/microchip_pfsoc.c | 2 +-
 hw/riscv/sifive_u.c        | 5 +++--
 hw/riscv/virt.c            | 2 +-
 include/hw/riscv/boot.h    | 2 +-
 6 files changed, 10 insertions(+), 9 deletions(-)

-- 
2.48.1