1 | Hi, all: | 1 | Hi, all: |
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2 | 2 | ||
3 | According to the "The RISC-V Instruction Set Manual Volume I: Unprivileged | 3 | I improve compatibility with RV32 and RV64 by adjusting the FIELD definition |
4 | Architecture" Version 20240411, Section 31.3.4 "Vector type register, vtype", | 4 | of vtype.vill. |
5 | and Table 40 "vtype register layout", this patch adds the definition for the | ||
6 | vill field of the vtype register. The bit position for vill is [63]. | ||
7 | 5 | ||
8 | This change ensures that our implementation remains in line with the latest | 6 | PATCH v1: |
9 | RISC-V specifications, thereby maintaining compatibility and correctness. | 7 | https://lore.kernel.org/qemu-devel/cover.1733922709.git.lc00631@tecorigin.com/T |
10 | 8 | ||
11 | Chao Liu (1): | 9 | Chao Liu (1): |
12 | target/riscv: add VILL field for vtype register macro definition | 10 | target/riscv: add VILL field for vtype register macro definition |
13 | 11 | ||
14 | target/riscv/cpu.h | 3 ++- | 12 | target/riscv/cpu.h | 3 ++- |
15 | 1 file changed, 2 insertions(+), 1 deletion(-) | 13 | 1 file changed, 2 insertions(+), 1 deletion(-) |
16 | 14 | ||
17 | -- | 15 | -- |
18 | 2.47.0 | 16 | 2.47.0 | diff view generated by jsdifflib |
... | ... | ||
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11 | FIELD(VTYPE, VTA, 6, 1) | 11 | FIELD(VTYPE, VTA, 6, 1) |
12 | FIELD(VTYPE, VMA, 7, 1) | 12 | FIELD(VTYPE, VMA, 7, 1) |
13 | FIELD(VTYPE, VEDIV, 8, 2) | 13 | FIELD(VTYPE, VEDIV, 8, 2) |
14 | -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) | 14 | -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) |
15 | +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12) | 15 | +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12) |
16 | +FIELD(VTYPE, VILL, 63, 1) | 16 | +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) |
17 | 17 | ||
18 | typedef struct PMUCTRState { | 18 | typedef struct PMUCTRState { |
19 | /* Current value of a counter */ | 19 | /* Current value of a counter */ |
20 | -- | 20 | -- |
21 | 2.47.0 | 21 | 2.47.0 | diff view generated by jsdifflib |