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Hi, all:
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Hi, all:
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According to the "The RISC-V Instruction Set Manual Volume I: Unprivileged
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I improve compatibility with RV32 and RV64 by adjusting the FIELD definition
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Architecture" Version 20240411, Section 31.3.4 "Vector type register, vtype",
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of vtype.vill.
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and Table 40 "vtype register layout", this patch adds the definition for the
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vill field of the vtype register. The bit position for vill is [63].
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This change ensures that our implementation remains in line with the latest
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PATCH v1:
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RISC-V specifications, thereby maintaining compatibility and correctness.
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https://lore.kernel.org/qemu-devel/cover.1733922709.git.lc00631@tecorigin.com/T
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Chao Liu (1):
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Chao Liu (1):
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target/riscv: add VILL field for vtype register macro definition
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target/riscv: add VILL field for vtype register macro definition
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target/riscv/cpu.h | 3 ++-
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target/riscv/cpu.h | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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1 file changed, 2 insertions(+), 1 deletion(-)
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--
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--
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2.47.0
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2.47.0
diff view generated by jsdifflib
...
...
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FIELD(VTYPE, VTA, 6, 1)
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FIELD(VTYPE, VTA, 6, 1)
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FIELD(VTYPE, VMA, 7, 1)
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FIELD(VTYPE, VMA, 7, 1)
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FIELD(VTYPE, VEDIV, 8, 2)
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FIELD(VTYPE, VEDIV, 8, 2)
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-FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
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-FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
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+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12)
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+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12)
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+FIELD(VTYPE, VILL, 63, 1)
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+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
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typedef struct PMUCTRState {
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typedef struct PMUCTRState {
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/* Current value of a counter */
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/* Current value of a counter */
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--
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--
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2.47.0
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2.47.0
diff view generated by jsdifflib