We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for ARM (and Aarch64) targets. We decided to
treat the (V)IRQ, (VI/VF)NMI, (V)FIQ and VSERR exceptions as interrupts
since they are, presumably, async in nature.
Signed-off-by: Julian Ganz <neither@nut.email>
---
target/arm/helper.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0a731a38e8..f636e216c8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -31,6 +31,7 @@
#endif
#include "cpregs.h"
#include "target/arm/gtimer.h"
+#include "qemu/plugin.h"
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
@@ -11147,6 +11148,24 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
}
}
+static void arm_do_plugin_vcpu_interrupt_cb(CPUState *cs)
+{
+ switch (cs->exception_index) {
+ case EXCP_IRQ:
+ case EXCP_VIRQ:
+ case EXCP_NMI:
+ case EXCP_VINMI:
+ case EXCP_FIQ:
+ case EXCP_VFIQ:
+ case EXCP_VFNMI:
+ case EXCP_VSERR:
+ qemu_plugin_vcpu_interrupt_cb(cs);
+ break;
+ default:
+ qemu_plugin_vcpu_exception_cb(cs);
+ }
+}
+
static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
{
/*
@@ -11819,6 +11838,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
arm_handle_psci_call(cpu);
qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
+ arm_do_plugin_vcpu_interrupt_cb(cs);
return;
}
@@ -11830,6 +11850,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
#ifdef CONFIG_TCG
if (cs->exception_index == EXCP_SEMIHOST) {
tcg_handle_semihosting(cs);
+ qemu_plugin_vcpu_semihosting_cb(cs);
return;
}
#endif
@@ -11855,6 +11876,8 @@ void arm_cpu_do_interrupt(CPUState *cs)
if (!kvm_enabled()) {
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
+
+ arm_do_plugin_vcpu_interrupt_cb(cs);
}
#endif /* !CONFIG_USER_ONLY */
--
2.45.2On Sat, 19 Oct 2024 at 17:39, Julian Ganz <neither@nut.email> wrote:
>
> We recently introduced API for registering callbacks for trap related
> events as well as the corresponding hook functions. Due to differences
> between architectures, the latter need to be called from target specific
> code.
>
> This change places hooks for ARM (and Aarch64) targets. We decided to
> treat the (V)IRQ, (VI/VF)NMI, (V)FIQ and VSERR exceptions as interrupts
> since they are, presumably, async in nature.
>
> Signed-off-by: Julian Ganz <neither@nut.email>
> ---
> target/arm/helper.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
This omits M-profile Arm CPUs (whose interrupt/exception
handling is rather more complicated, and lives in
m_helper.c.)
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 0a731a38e8..f636e216c8 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -31,6 +31,7 @@
> #endif
> #include "cpregs.h"
> #include "target/arm/gtimer.h"
> +#include "qemu/plugin.h"
>
> #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
>
> @@ -11147,6 +11148,24 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
> }
> }
>
> +static void arm_do_plugin_vcpu_interrupt_cb(CPUState *cs)
> +{
> + switch (cs->exception_index) {
> + case EXCP_IRQ:
> + case EXCP_VIRQ:
> + case EXCP_NMI:
> + case EXCP_VINMI:
> + case EXCP_FIQ:
> + case EXCP_VFIQ:
> + case EXCP_VFNMI:
> + case EXCP_VSERR:
> + qemu_plugin_vcpu_interrupt_cb(cs);
> + break;
> + default:
> + qemu_plugin_vcpu_exception_cb(cs);
> + }
> +}
> +
> static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
> {
> /*
> @@ -11819,6 +11838,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
> arm_handle_psci_call(cpu);
> qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
> + arm_do_plugin_vcpu_interrupt_cb(cs);
This isn't really an interrupt or exception -- it's
more like the semihosting, where the guest does an HVC
or SMC instruction and QEMU handles it by emulating it
as if it were firmware. Maybe it would be better to
name the "semihosting" plugin callbacks something more
generic and include this kind of case in them ?
> return;
> }
>
> @@ -11830,6 +11850,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> #ifdef CONFIG_TCG
> if (cs->exception_index == EXCP_SEMIHOST) {
> tcg_handle_semihosting(cs);
> + qemu_plugin_vcpu_semihosting_cb(cs);
> return;
> }
> #endif
> @@ -11855,6 +11876,8 @@ void arm_cpu_do_interrupt(CPUState *cs)
> if (!kvm_enabled()) {
> cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
> }
> +
> + arm_do_plugin_vcpu_interrupt_cb(cs);
thanks
-- PMM
Thanks for the quick reply!
October 21, 2024 at 2:58 PM, Peter Maydell wrote:
> This omits M-profile Arm CPUs (whose interrupt/exception
> handling is rather more complicated, and lives in
> m_helper.c.)
Yes, I forgot about the M-profile. I'll include those changes wiith the
next patch-series.
> > @@ -11819,6 +11838,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> > if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
> > arm_handle_psci_call(cpu);
> > qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
> > + arm_do_plugin_vcpu_interrupt_cb(cs);
> >
> This isn't really an interrupt or exception -- it's
> more like the semihosting, where the guest does an HVC
> or SMC instruction and QEMU handles it by emulating it
> as if it were firmware. Maybe it would be better to
> name the "semihosting" plugin callbacks something more
> generic and include this kind of case in them ?
Oh, good to know. The only term for something like this (which also
includes semihosting) that comes to mind would be "host call". But that
may be confusing when talking about emulated vs simulated hypervisors?
Regards,
Julian
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