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[RFC PATCH V2 5/5] hw/loongarch: Add KVM pch msi device support

Xianglai Li posted 5 patches 2 months, 2 weeks ago
There is a newer version of this series
[RFC PATCH V2 5/5] hw/loongarch: Add KVM pch msi device support
Posted by Xianglai Li 2 months, 2 weeks ago 
Added pch_msi interrupt controller handling
during kernel emulation of irq chip.

Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
---
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Song Gao <gaosong@loongson.cn>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhuacai@kernel.org>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Cc: kvm@vger.kernel.org
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Xianglai Li <lixianglai@loongson.cn>

 hw/intc/loongarch_pch_msi.c | 42 +++++++++++++++++++++++++++----------
 hw/loongarch/virt.c         | 26 +++++++++++++----------
 target/loongarch/kvm/kvm.c  |  1 -
 3 files changed, 46 insertions(+), 23 deletions(-)

diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
index ecf3ed0267..bab6f852f8 100644
--- a/hw/intc/loongarch_pch_msi.c
+++ b/hw/intc/loongarch_pch_msi.c
@@ -2,7 +2,7 @@
 /*
  * QEMU Loongson 7A1000 msi interrupt controller.
  *
- * Copyright (C) 2021 Loongson Technology Corporation Limited
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
  */
 
 #include "qemu/osdep.h"
@@ -14,6 +14,8 @@
 #include "hw/misc/unimp.h"
 #include "migration/vmstate.h"
 #include "trace.h"
+#include "sysemu/kvm.h"
+#include "hw/loongarch/virt.h"
 
 static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
 {
@@ -26,14 +28,24 @@ static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
     LoongArchPCHMSI *s = (LoongArchPCHMSI *)opaque;
     int irq_num;
 
-    /*
-     * vector number is irq number from upper extioi intc
-     * need subtract irq base to get msi vector offset
-     */
-    irq_num = (val & 0xff) - s->irq_base;
-    trace_loongarch_msi_set_irq(irq_num);
-    assert(irq_num < s->irq_num);
-    qemu_set_irq(s->pch_msi_irq[irq_num], 1);
+    MSIMessage msg = {
+        .address = addr,
+        .data = val,
+    };
+
+    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+        kvm_irqchip_send_msi(kvm_state, msg);
+    } else {
+        /*
+         * vector number is irq number from upper extioi intc
+         * need subtract irq base to get msi vector offset
+         */
+        irq_num = (val & 0xff) - s->irq_base;
+        trace_loongarch_msi_set_irq(irq_num);
+        assert(irq_num < s->irq_num);
+
+        qemu_set_irq(s->pch_msi_irq[irq_num], 1);
+    }
 }
 
 static const MemoryRegionOps loongarch_pch_msi_ops = {
@@ -45,8 +57,16 @@ static const MemoryRegionOps loongarch_pch_msi_ops = {
 static void pch_msi_irq_handler(void *opaque, int irq, int level)
 {
     LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
-
-    qemu_set_irq(s->pch_msi_irq[irq], level);
+    MSIMessage msg = {
+        .address = 0,
+        .data = irq,
+    };
+
+    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+        kvm_irqchip_send_msi(kvm_state, msg);
+    } else {
+        qemu_set_irq(s->pch_msi_irq[irq], level);
+    }
 }
 
 static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index db0c08899b..b42cf7e5af 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -887,24 +887,28 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
         for (i = 0; i < num; i++) {
             qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
         }
+    }
 
-        /* Add PCH PIC node */
-        fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
+    /* Add PCH PIC node */
+    fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
 
-        pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
-        start   =  num;
-        num = EXTIOI_IRQS - start;
-        qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
-        qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
-        d = SYS_BUS_DEVICE(pch_msi);
-        sysbus_realize_and_unref(d, &error_fatal);
-        sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
+    pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
+    num = VIRT_PCH_PIC_IRQ_NUM;
+    start   =  num;
+    num = EXTIOI_IRQS - start;
+    qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
+    qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
+    d = SYS_BUS_DEVICE(pch_msi);
+    sysbus_realize_and_unref(d, &error_fatal);
+
+    if (!(kvm_enabled() && kvm_irqchip_in_kernel())) {
+        /* Connect pch_msi irqs to extioi */
         for (i = 0; i < num; i++) {
-            /* Connect pch_msi irqs to extioi */
             qdev_connect_gpio_out(DEVICE(d), i,
                                   qdev_get_gpio_in(extioi, i + start));
         }
     }
+    sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
 
     /* Add PCH MSI node */
     fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index c07dcfd85f..e1be6a6959 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -719,7 +719,6 @@ int kvm_arch_get_default_type(MachineState *ms)
 
 int kvm_arch_init(MachineState *ms, KVMState *s)
 {
-    s->kernel_irqchip_allowed = false;
     cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
     return 0;
 }
-- 
2.39.1
Re: [RFC PATCH V2 5/5] hw/loongarch: Add KVM pch msi device support
Posted by maobibo 2 months, 1 week ago 
Hi Xianglai,

I do not find any usage about function kvm_irqchip_commit_routes() in 
your patch-set, do I miss something?

Regards
Bibo Mao

On 2024/9/10 下午8:18, Xianglai Li wrote:
> Added pch_msi interrupt controller handling
> during kernel emulation of irq chip.
> 
> Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
> ---
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Song Gao <gaosong@loongson.cn>
> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Cc: Huacai Chen <chenhuacai@kernel.org>
> Cc: "Michael S. Tsirkin" <mst@redhat.com>
> Cc: Cornelia Huck <cohuck@redhat.com>
> Cc: kvm@vger.kernel.org
> Cc: Bibo Mao <maobibo@loongson.cn>
> Cc: Xianglai Li <lixianglai@loongson.cn>
> 
>   hw/intc/loongarch_pch_msi.c | 42 +++++++++++++++++++++++++++----------
>   hw/loongarch/virt.c         | 26 +++++++++++++----------
>   target/loongarch/kvm/kvm.c  |  1 -
>   3 files changed, 46 insertions(+), 23 deletions(-)
> 
> diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
> index ecf3ed0267..bab6f852f8 100644
> --- a/hw/intc/loongarch_pch_msi.c
> +++ b/hw/intc/loongarch_pch_msi.c
> @@ -2,7 +2,7 @@
>   /*
>    * QEMU Loongson 7A1000 msi interrupt controller.
>    *
> - * Copyright (C) 2021 Loongson Technology Corporation Limited
> + * Copyright (C) 2024 Loongson Technology Corporation Limited
>    */
>   
>   #include "qemu/osdep.h"
> @@ -14,6 +14,8 @@
>   #include "hw/misc/unimp.h"
>   #include "migration/vmstate.h"
>   #include "trace.h"
> +#include "sysemu/kvm.h"
> +#include "hw/loongarch/virt.h"
>   
>   static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
>   {
> @@ -26,14 +28,24 @@ static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
>       LoongArchPCHMSI *s = (LoongArchPCHMSI *)opaque;
>       int irq_num;
>   
> -    /*
> -     * vector number is irq number from upper extioi intc
> -     * need subtract irq base to get msi vector offset
> -     */
> -    irq_num = (val & 0xff) - s->irq_base;
> -    trace_loongarch_msi_set_irq(irq_num);
> -    assert(irq_num < s->irq_num);
> -    qemu_set_irq(s->pch_msi_irq[irq_num], 1);
> +    MSIMessage msg = {
> +        .address = addr,
> +        .data = val,
> +    };
> +
> +    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
> +        kvm_irqchip_send_msi(kvm_state, msg);
> +    } else {
> +        /*
> +         * vector number is irq number from upper extioi intc
> +         * need subtract irq base to get msi vector offset
> +         */
> +        irq_num = (val & 0xff) - s->irq_base;
> +        trace_loongarch_msi_set_irq(irq_num);
> +        assert(irq_num < s->irq_num);
> +
> +        qemu_set_irq(s->pch_msi_irq[irq_num], 1);
> +    }
>   }
>   
>   static const MemoryRegionOps loongarch_pch_msi_ops = {
> @@ -45,8 +57,16 @@ static const MemoryRegionOps loongarch_pch_msi_ops = {
>   static void pch_msi_irq_handler(void *opaque, int irq, int level)
>   {
>       LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
> -
> -    qemu_set_irq(s->pch_msi_irq[irq], level);
> +    MSIMessage msg = {
> +        .address = 0,
> +        .data = irq,
> +    };
> +
> +    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
> +        kvm_irqchip_send_msi(kvm_state, msg);
> +    } else {
> +        qemu_set_irq(s->pch_msi_irq[irq], level);
> +    }
>   }
>   
>   static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index db0c08899b..b42cf7e5af 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -887,24 +887,28 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
>           for (i = 0; i < num; i++) {
>               qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
>           }
> +    }
>   
> -        /* Add PCH PIC node */
> -        fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
> +    /* Add PCH PIC node */
> +    fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
>   
> -        pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
> -        start   =  num;
> -        num = EXTIOI_IRQS - start;
> -        qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
> -        qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
> -        d = SYS_BUS_DEVICE(pch_msi);
> -        sysbus_realize_and_unref(d, &error_fatal);
> -        sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
> +    pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
> +    num = VIRT_PCH_PIC_IRQ_NUM;
> +    start   =  num;
> +    num = EXTIOI_IRQS - start;
> +    qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
> +    qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
> +    d = SYS_BUS_DEVICE(pch_msi);
> +    sysbus_realize_and_unref(d, &error_fatal);
> +
> +    if (!(kvm_enabled() && kvm_irqchip_in_kernel())) {
> +        /* Connect pch_msi irqs to extioi */
>           for (i = 0; i < num; i++) {
> -            /* Connect pch_msi irqs to extioi */
>               qdev_connect_gpio_out(DEVICE(d), i,
>                                     qdev_get_gpio_in(extioi, i + start));
>           }
>       }
> +    sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
>   
>       /* Add PCH MSI node */
>       fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
> diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
> index c07dcfd85f..e1be6a6959 100644
> --- a/target/loongarch/kvm/kvm.c
> +++ b/target/loongarch/kvm/kvm.c
> @@ -719,7 +719,6 @@ int kvm_arch_get_default_type(MachineState *ms)
>   
>   int kvm_arch_init(MachineState *ms, KVMState *s)
>   {
> -    s->kernel_irqchip_allowed = false;
>       cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
>       return 0;
>   }
>

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