On Sat, May 14, 2022 at 4:29 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> c.f.
> <https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00229.html>
>
> This patchset is functionally equivalent to v1 but fixes commit titles.
>
>
>
>
> Tsukasa OI (2):
> hw/riscv: Make CPU config error handling generous (virt/spike)
> hw/riscv: Make CPU config error handling generous
> (sifive_e/u/opentitan)
>
> hw/riscv/opentitan.c | 2 +-
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 4 ++--
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 2 +-
> 5 files changed, 6 insertions(+), 6 deletions(-)
Thanks!
Applied to riscv-to-apply.next
Alistair
>
>
> base-commit: 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab
> --
> 2.34.1
>