[v2] target/riscv: ISA string conversion fix and enhancement

[PATCH v2 0/2] target/riscv: ISA string conversion fix and enhancement

Tsukasa OI posted 2 patches 1 year, 11 months ago

Diff against v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1652181972.git.research._5Ftrasio@irq.a4lg.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

target/riscv/cpu.c | 9 ++++++---
target/riscv/cpu.h | 2 ++
2 files changed, 8 insertions(+), 3 deletions(-)

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[PATCH v2 0/2] target/riscv: ISA string conversion fix and enhancement

Posted by Tsukasa OI 1 year, 11 months ago

Hello,

There is two issues related to RISC-V ISA extension string
I want to be fixed before QEMU 7.1 release.

This is PATCH v2.

For details, see cover letter of PATCH v1.
<https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg03817.html>



PATCH v1 -> PATCH v2:

I decided to "move" Zhinx*, not to remove them tentativelly.

Because, although I disagree with Weiwei's opinion (on canonical
ordering, Z* multi-letter extensions are ordered by second character;
that should reflect closely related single-letter extension but that
didn't happened on Zhinx*), ordering of "H" is reviewed and going to be
right after "V".

I considered this is safe enough (despite its "unratified" status):

1.  Zhinx and Zhinxmin are minor extensions
2.  Extension ordering is going to be not that important in the future
    (by upcoming rules) but we have reasons to make extension ordering
    canonical as possible for toolchain compatibility (for now).




Tsukasa OI (2):
  target/riscv: Move Zhinx* extensions on ISA string
  target/riscv: Add short-isa-string option

 target/riscv/cpu.c | 9 ++++++---
 target/riscv/cpu.h | 2 ++
 2 files changed, 8 insertions(+), 3 deletions(-)


base-commit: 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab
-- 
2.34.1

Re: [PATCH v2 0/2] target/riscv: ISA string conversion fix and enhancement

Posted by Alistair Francis 1 year, 11 months ago

On Tue, May 10, 2022 at 9:29 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Hello,
>
> There is two issues related to RISC-V ISA extension string
> I want to be fixed before QEMU 7.1 release.
>
> This is PATCH v2.
>
> For details, see cover letter of PATCH v1.
> <https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg03817.html>
>
>
>
> PATCH v1 -> PATCH v2:
>
> I decided to "move" Zhinx*, not to remove them tentativelly.
>
> Because, although I disagree with Weiwei's opinion (on canonical
> ordering, Z* multi-letter extensions are ordered by second character;
> that should reflect closely related single-letter extension but that
> didn't happened on Zhinx*), ordering of "H" is reviewed and going to be
> right after "V".
>
> I considered this is safe enough (despite its "unratified" status):
>
> 1.  Zhinx and Zhinxmin are minor extensions
> 2.  Extension ordering is going to be not that important in the future
>     (by upcoming rules) but we have reasons to make extension ordering
>     canonical as possible for toolchain compatibility (for now).
>
>
>
>
> Tsukasa OI (2):
>   target/riscv: Move Zhinx* extensions on ISA string
>   target/riscv: Add short-isa-string option
>
>  target/riscv/cpu.c | 9 ++++++---
>  target/riscv/cpu.h | 2 ++
>  2 files changed, 8 insertions(+), 3 deletions(-)

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>
> base-commit: 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab
> --
> 2.34.1
>