[v2] target/riscv: misa to ISA string conversion fix

[PATCH v2 0/1] target/riscv: misa to ISA string conversion fix

Tsukasa OI posted 1 patch 3 years, 8 months ago

Diff against v1
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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

target/riscv/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

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[PATCH v2 0/1] target/riscv: misa to ISA string conversion fix

Posted by Tsukasa OI 3 years, 8 months ago

[v1] https://lists.gnu.org/archive/html/qemu-devel/2022-03/msg06350.html

S and U are misa bits but not extensions (instead, they are supported
privilege modes).  Thus, they should not be copied to the ISA string.

[CHANGES: v1 -> v2]

I also removed almost all reserved/dropped single-letter "extensions"
from the list.

-   "B": Not going to be a single-letter extension (misa.B is reserved).
-   "J": Not going to be a single-letter extension (misa.J is reserved).
-   "K": Not going to be a single-letter extension (misa.K is reserved).
-   "L": Dropped.
-   "N": Dropped.
-   "T": Dropped.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>




Tsukasa OI (1):
  target/riscv: misa to ISA string conversion fix

 target/riscv/cpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)


base-commit: 3d31fe4d662f13c70eb7e87f29513623ccd76322
-- 
2.32.0