[PATCH v4 00/16] RISC-V: Start to remove xlen preprocess

Alistair Francis posted 16 patches 3 years, 4 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1608142916.git.alistair.francis@wdc.com
Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
include/hw/riscv/boot.h   |  14 +--
include/hw/riscv/spike.h  |   6 --
include/hw/riscv/virt.h   |   6 --
target/riscv/cpu.h        |   8 ++
target/riscv/cpu_bits.h   |   4 +-
target/riscv/helper.h     |  24 ++----
hw/riscv/boot.c           |  70 ++++++++-------
hw/riscv/sifive_u.c       |  59 +++++++------
hw/riscv/spike.c          |  52 +++++------
hw/riscv/virt.c           |  39 +++++----
target/riscv/cpu.c        |  84 ++++++++++++------
target/riscv/cpu_helper.c |  12 +--
target/riscv/csr.c        | 176 ++++++++++++++++++++------------------
target/riscv/fpu_helper.c |   8 --
14 files changed, 299 insertions(+), 263 deletions(-)
[PATCH v4 00/16] RISC-V: Start to remove xlen preprocess
Posted by Alistair Francis 3 years, 4 months ago
The RISC-V QEMU port currently has lot of preprocessor directives that
check if we are targetting a 32-bit or 64-bit CPU. This means that the
64-bit RISC-V target can not run 32-bit CPUs. This is different to most
other QEMU architectures and doesn't allow us to mix xlens (such as when
running Hypervisors with different xlen guests).

This series is a step toward removing some of those to allow us to use
32-bit CPUs on 64-bit RISC-V targets.

v4:
 - Add a commit that converts the machine 32-bit check to use the CPU
v3:
 - Address Richard's comments
v2:
 - Rebase on the latest RISC-V tree

Alistair Francis (16):
  hw/riscv: Expand the is 32-bit check to support more CPUs
  target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
  riscv: spike: Remove target macro conditionals
  riscv: virt: Remove target macro conditionals
  hw/riscv: boot: Remove compile time XLEN checks
  hw/riscv: virt: Remove compile time XLEN checks
  hw/riscv: spike: Remove compile time XLEN checks
  hw/riscv: sifive_u: Remove compile time XLEN checks
  target/riscv: fpu_helper: Match function defs in HELPER macros
  target/riscv: Add a riscv_cpu_is_32bit() helper function
  target/riscv: Specify the XLEN for CPUs
  target/riscv: cpu: Remove compile time XLEN checks
  target/riscv: cpu_helper: Remove compile time XLEN checks
  target/riscv: csr: Remove compile time XLEN checks
  target/riscv: cpu: Set XLEN independently from target
  hw/riscv: Use the CPU to determine if 32-bit

 include/hw/riscv/boot.h   |  14 +--
 include/hw/riscv/spike.h  |   6 --
 include/hw/riscv/virt.h   |   6 --
 target/riscv/cpu.h        |   8 ++
 target/riscv/cpu_bits.h   |   4 +-
 target/riscv/helper.h     |  24 ++----
 hw/riscv/boot.c           |  70 ++++++++-------
 hw/riscv/sifive_u.c       |  59 +++++++------
 hw/riscv/spike.c          |  52 +++++------
 hw/riscv/virt.c           |  39 +++++----
 target/riscv/cpu.c        |  84 ++++++++++++------
 target/riscv/cpu_helper.c |  12 +--
 target/riscv/csr.c        | 176 ++++++++++++++++++++------------------
 target/riscv/fpu_helper.c |   8 --
 14 files changed, 299 insertions(+), 263 deletions(-)

-- 
2.29.2