[v3] Fix the Hypervisor access functions

[PATCH v3 0/7] Fix the Hypervisor access functions

Alistair Francis posted 7 patches 3 years, 5 months ago

Diff against v1 v2 v4
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1604432950.git.alistair.francis@wdc.com

Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>

There is a newer version of this series

target/riscv/cpu-param.h                |  10 +-
target/riscv/cpu.h                      |  43 ++--
target/riscv/cpu_bits.h                 |  20 +-
target/riscv/helper.h                   |   5 +-
target/riscv/cpu.c                      |   8 +-
target/riscv/cpu_helper.c               |  99 ++++------
target/riscv/csr.c                      |  18 +-
target/riscv/op_helper.c                | 135 +------------
target/riscv/translate.c                |   2 +
target/riscv/insn_trans/trans_rvh.c.inc | 248 +++++++++++++++---------
10 files changed, 260 insertions(+), 328 deletions(-)

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[PATCH v3 0/7] Fix the Hypervisor access functions

Posted by Alistair Francis 3 years, 5 months ago

Richard pointed out that the Hypervisor access functions don't work
correctly, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg751540.html.
This seris fixes them up by adding a new MMU index for the virtualised
state.

v3:
 - Only set the virtualised MMU mode for HLX ops
v2:
 - Use only 6 MMU modes instead of 8

Alistair Francis (6):
  target/riscv: Add a virtualised MMU Mode
  target/riscv: Set the virtualised MMU mode when doing hyp accesses
  target/riscv: Remove the HS_TWO_STAGE flag
  target/riscv: Remove the hyp load and store functions
  target/riscv: Remove the Hypervisor access check function
  target/riscv: Split the Hypervisor execute load helpers

Yifei Jiang (1):
  target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit

 target/riscv/cpu-param.h                |  10 +-
 target/riscv/cpu.h                      |  43 ++--
 target/riscv/cpu_bits.h                 |  20 +-
 target/riscv/helper.h                   |   5 +-
 target/riscv/cpu.c                      |   8 +-
 target/riscv/cpu_helper.c               |  99 ++++------
 target/riscv/csr.c                      |  18 +-
 target/riscv/op_helper.c                | 135 +------------
 target/riscv/translate.c                |   2 +
 target/riscv/insn_trans/trans_rvh.c.inc | 248 +++++++++++++++---------
 10 files changed, 260 insertions(+), 328 deletions(-)

-- 
2.28.0