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[PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1

Alistair Francis posted 13 patches 3 years, 8 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1597259519.git.alistair.francis@wdc.com
Maintainers: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Alistair Francis <Alistair.Francis@wdc.com>
target/riscv/cpu.h                      |   2 +
target/riscv/cpu_bits.h                 |  25 +-
target/riscv/helper.h                   |   4 +
target/riscv/insn32-64.decode           |   5 +
target/riscv/insn32.decode              |  11 +
target/riscv/cpu_helper.c               | 123 +++++----
target/riscv/csr.c                      | 171 ++++++++++--
target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
target/riscv/op_helper.c                | 176 +++++++++++-
target/riscv/translate.c                |  10 -
10 files changed, 761 insertions(+), 108 deletions(-)
[PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
Posted by Alistair Francis 3 years, 8 months ago 
This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6.1 draft implementation.

THis includes support for the new 2-stage lookup instructions and the new
CSRs.

It also includes the new 0.6.1 support for the virtual instruction
fault.

This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
Linux guests.

v3:
 - Rebase on master
v2:
 - Update to v0.6.1



Alistair Francis (13):
  target/riscv: Allow setting a two-stage lookup in the virt status
  target/riscv: Allow generating hlv/hlvx/hsv instructions
  target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
  target/riscv: Don't allow guest to write to htinst
  target/riscv: Convert MSTATUS MTL to GVA
  target/riscv: Fix the interrupt cause code
  target/riscv: Update the Hypervisor trap return/entry
  target/riscv: Update the CSRs to the v0.6 Hyp extension
  target/riscv: Only support a single VSXL length
  target/riscv: Only support little endian guests
  target/riscv: Support the v0.6 Hypervisor extension CRSs
  target/riscv: Return the exception from invalid CSR accesses
  target/riscv: Support the Virtual Instruction fault

 target/riscv/cpu.h                      |   2 +
 target/riscv/cpu_bits.h                 |  25 +-
 target/riscv/helper.h                   |   4 +
 target/riscv/insn32-64.decode           |   5 +
 target/riscv/insn32.decode              |  11 +
 target/riscv/cpu_helper.c               | 123 +++++----
 target/riscv/csr.c                      | 171 ++++++++++--
 target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
 target/riscv/op_helper.c                | 176 +++++++++++-
 target/riscv/translate.c                |  10 -
 10 files changed, 761 insertions(+), 108 deletions(-)

-- 
2.27.0
Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
Posted by LIU Zhiwei 3 years, 8 months ago 

On 2020/8/13 3:13, Alistair Francis wrote:
> This series updates the experimental QEMU RISC-V Hypervisor spec to the
> v0.6.1 draft implementation.
>
> THis includes support for the new 2-stage lookup instructions and the new
> CSRs.
>
> It also includes the new 0.6.1 support for the virtual instruction
> fault.
>
> This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
> Linux guests.
Hi Alistair,

I am reading Christoper Dall's article on ARM virtualization.  As far as 
I can see,  Xvisor is type 1 hypervisor.

I want to  try this patch set. Could you share the method? Thanks very much.

Best Regards,
Zhiwei
> v3:
>   - Rebase on master
> v2:
>   - Update to v0.6.1
>
>
>
> Alistair Francis (13):
>    target/riscv: Allow setting a two-stage lookup in the virt status
>    target/riscv: Allow generating hlv/hlvx/hsv instructions
>    target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
>    target/riscv: Don't allow guest to write to htinst
>    target/riscv: Convert MSTATUS MTL to GVA
>    target/riscv: Fix the interrupt cause code
>    target/riscv: Update the Hypervisor trap return/entry
>    target/riscv: Update the CSRs to the v0.6 Hyp extension
>    target/riscv: Only support a single VSXL length
>    target/riscv: Only support little endian guests
>    target/riscv: Support the v0.6 Hypervisor extension CRSs
>    target/riscv: Return the exception from invalid CSR accesses
>    target/riscv: Support the Virtual Instruction fault
>
>   target/riscv/cpu.h                      |   2 +
>   target/riscv/cpu_bits.h                 |  25 +-
>   target/riscv/helper.h                   |   4 +
>   target/riscv/insn32-64.decode           |   5 +
>   target/riscv/insn32.decode              |  11 +
>   target/riscv/cpu_helper.c               | 123 +++++----
>   target/riscv/csr.c                      | 171 ++++++++++--
>   target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
>   target/riscv/op_helper.c                | 176 +++++++++++-
>   target/riscv/translate.c                |  10 -
>   10 files changed, 761 insertions(+), 108 deletions(-)
>
Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
Posted by Alistair Francis 3 years, 8 months ago 
On Wed, Aug 12, 2020 at 7:26 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
>
> On 2020/8/13 3:13, Alistair Francis wrote:
> > This series updates the experimental QEMU RISC-V Hypervisor spec to the
> > v0.6.1 draft implementation.
> >
> > THis includes support for the new 2-stage lookup instructions and the new
> > CSRs.
> >
> > It also includes the new 0.6.1 support for the virtual instruction
> > fault.
> >
> > This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
> > Linux guests.
> Hi Alistair,
>
> I am reading Christoper Dall's article on ARM virtualization.  As far as
> I can see,  Xvisor is type 1 hypervisor.

Yep, it's a bare metal Hypervisor.

>
> I want to  try this patch set. Could you share the method? Thanks very much.

There are some details in the origins submission, you can see them
here: https://patchew.org/QEMU/cover.1580518859.git.alistair.francis@wdc.com/

I'm also working on improving the support in meta-virtualisation to
help as well.

Thanks for helping test.

Alistair

>
> Best Regards,
> Zhiwei
> > v3:
> >   - Rebase on master
> > v2:
> >   - Update to v0.6.1
> >
> >
> >
> > Alistair Francis (13):
> >    target/riscv: Allow setting a two-stage lookup in the virt status
> >    target/riscv: Allow generating hlv/hlvx/hsv instructions
> >    target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
> >    target/riscv: Don't allow guest to write to htinst
> >    target/riscv: Convert MSTATUS MTL to GVA
> >    target/riscv: Fix the interrupt cause code
> >    target/riscv: Update the Hypervisor trap return/entry
> >    target/riscv: Update the CSRs to the v0.6 Hyp extension
> >    target/riscv: Only support a single VSXL length
> >    target/riscv: Only support little endian guests
> >    target/riscv: Support the v0.6 Hypervisor extension CRSs
> >    target/riscv: Return the exception from invalid CSR accesses
> >    target/riscv: Support the Virtual Instruction fault
> >
> >   target/riscv/cpu.h                      |   2 +
> >   target/riscv/cpu_bits.h                 |  25 +-
> >   target/riscv/helper.h                   |   4 +
> >   target/riscv/insn32-64.decode           |   5 +
> >   target/riscv/insn32.decode              |  11 +
> >   target/riscv/cpu_helper.c               | 123 +++++----
> >   target/riscv/csr.c                      | 171 ++++++++++--
> >   target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
> >   target/riscv/op_helper.c                | 176 +++++++++++-
> >   target/riscv/translate.c                |  10 -
> >   10 files changed, 761 insertions(+), 108 deletions(-)
> >
>

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