On 7/25/20 7:34 AM, Alistair Francis wrote:
> After a claim or a priority change we need to update the pending
> interrupts. This is based on the same patch for the SiFive PLIC:
> 55765822804f5a58594e "riscv: plic: Add a couple of mising
> sifive_plic_update calls"
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/intc/ibex_plic.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index 41079518c6..578edd2ce0 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> s->pending[pending_num] &= ~(1 << (s->claim % 32));
>
> ret = s->claim;
> +
> + /* Update the interrupt status after the claim */
> + ibex_plic_update(s);
> }
>
> return ret;
> @@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
> } else if (addr_between(addr, s->priority_base, s->priority_num)) {
> uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
> s->priority[irq] = value & 7;
> + ibex_plic_update(s);
> } else if (addr_between(addr, s->enable_base, s->enable_num)) {
> uint32_t enable_reg = (addr - s->enable_base) / 4;
>
>