[PATCH v3 0/3] Fix some PMP implementation

Zong Li posted 3 patches 5 years, 3 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1595335112.git.zong.li@sifive.com
Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>
target/riscv/cpu_helper.c | 3 ++-
target/riscv/csr.c        | 2 +-
target/riscv/pmp.c        | 8 ++++++++
3 files changed, 11 insertions(+), 2 deletions(-)
[PATCH v3 0/3] Fix some PMP implementation
Posted by Zong Li 5 years, 3 months ago
This patch set contains the fixes for wrong index of pmpcfg CSR on rv64,
and the pmp range in CSR function table. After 3rd version of this patch
series, we also fix the PMP wrong checking problem.

Changed in v3:
 - Refine the implementation. Suggested by Bin Meng.
 - Add fix for PMP wrong checking

Changed in v2:
 - Move out the shifting operation from loop. Suggested by Bin Meng.

Zong Li (3):
  target/riscv: Fix the range of pmpcfg of CSR funcion table
  target/riscv/pmp.c: Fix the index offset on RV64
  target/riscv: Fix the translation of physical address

 target/riscv/cpu_helper.c | 3 ++-
 target/riscv/csr.c        | 2 +-
 target/riscv/pmp.c        | 8 ++++++++
 3 files changed, 11 insertions(+), 2 deletions(-)

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2.27.0