[v1] A few RISC-V fixes

[PATCH v1 0/3] A few RISC-V fixes

Alistair Francis posted 3 patches 3 years, 10 months ago

Diff against v2
Download series mbox

Test FreeBSD passed

Test docker-quick@centos7 passed

Test checkpatch passed

Test docker-mingw@fedora passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1593547870.git.alistair.francis@wdc.com

Maintainers: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Paolo Bonzini <pbonzini@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, "Marc-André Lureau" <marcandre.lureau@redhat.com>

There is a newer version of this series

include/hw/char/ibex_uart.h |  2 ++
hw/char/ibex_uart.c         | 19 ++++++++++++++++++-
hw/riscv/sifive_clint.c     |  2 +-
target/riscv/translate.c    |  2 +-
4 files changed, 22 insertions(+), 3 deletions(-)

Expand all Fold all

[PATCH v1 0/3] A few RISC-V fixes

Posted by Alistair Francis 3 years, 10 months ago

This series has a few fixes for RISC-V.



Alistair Francis (3):
  hw/char: Convert the Ibex UART to use the qdev Clock model
  hw/riscv: Allow 64 bit access to SiFive CLINT
  target/riscv: Regen floating point rounding mode in dynamic mode

 include/hw/char/ibex_uart.h |  2 ++
 hw/char/ibex_uart.c         | 19 ++++++++++++++++++-
 hw/riscv/sifive_clint.c     |  2 +-
 target/riscv/translate.c    |  2 +-
 4 files changed, 22 insertions(+), 3 deletions(-)

-- 
2.27.0