[v1] hw/riscv: Add a serial property to the sifive_u machine

[PATCH v1 0/3] hw/riscv: Add a serial property to the sifive_u machine

Alistair Francis posted 3 patches 5 years, 8 months ago

Diff against v2
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1583285287.git.alistair.francis@wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>

There is a newer version of this series

hw/riscv/sifive_u.c         | 135 +++++++++++++++++++++---------------
include/hw/riscv/sifive_u.h |   3 +
2 files changed, 84 insertions(+), 54 deletions(-)

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[PATCH v1 0/3] hw/riscv: Add a serial property to the sifive_u machine

Posted by Alistair Francis 5 years, 8 months ago

At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.

A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.

Alistair Francis (2):
  riscv/sifive_u: Fix up file ordering
  riscv/sifive_u: Add a serial property to the sifive_u SoC

Bin Meng (1):
  riscv/sifive_u: Add a serial property to the sifive_u machine

 hw/riscv/sifive_u.c         | 135 +++++++++++++++++++++---------------
 include/hw/riscv/sifive_u.h |   3 +
 2 files changed, 84 insertions(+), 54 deletions(-)

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2.25.1