On Mon, 09 Dec 2019 10:10:58 PST (-0800), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 4 ++++
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 18 ++++++++++++++++++
> 3 files changed, 25 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bab938103d..a73292cd20 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -117,6 +117,8 @@ struct CPURISCVState {
>
> #ifndef CONFIG_USER_ONLY
> target_ulong priv;
> + /* This contains QEMU specific information about the virt state. */
> + target_ulong virt;
> target_ulong resetvec;
>
> target_ulong mhartid;
> @@ -269,6 +271,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
> bool riscv_cpu_fp_enabled(CPURISCVState *env);
> +bool riscv_cpu_virt_enabled(CPURISCVState *env);
> +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
> int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
> hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index eeaa03c0f8..2cdb0de4fe 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -430,6 +430,9 @@
> #define PRV_H 2 /* Reserved */
> #define PRV_M 3
>
> +/* Virtulisation Register Fields */
> +#define VIRT_ONOFF 1
> +
> /* RV32 satp CSR field masks */
> #define SATP32_MODE 0x80000000
> #define SATP32_ASID 0x7fc00000
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index c201919c54..046f3549cc 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
> return false;
> }
>
> +bool riscv_cpu_virt_enabled(CPURISCVState *env)
> +{
> + if (!riscv_has_ext(env, RVH)) {
> + return false;
> + }
> +
> + return get_field(env->virt, VIRT_ONOFF);
> +}
> +
> +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
> +{
> + if (!riscv_has_ext(env, RVH)) {
> + return;
> + }
> +
> + env->virt = set_field(env->virt, VIRT_ONOFF, enable);
> +}
> +
> int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
> {
> CPURISCVState *env = &cpu->env;
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>