On Mon, 09 Dec 2019 10:12:06 PST (-0800), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_helper.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 43c6629014..aa033b8590 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -841,6 +841,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
> target_ulong deleg = async ? env->mideleg : env->medeleg;
> target_ulong tval = 0;
> + target_ulong htval = 0;
> + target_ulong mtval2 = 0;
>
> if (!async) {
> /* set tval to badaddr for traps with address information */
> @@ -900,6 +902,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> riscv_cpu_virt_enabled(env));
>
> + htval = env->guest_phys_fault_addr;
> +
> riscv_cpu_set_virt_enabled(env, 0);
> riscv_cpu_set_force_hs_excep(env, 0);
> } else {
> @@ -910,6 +914,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> get_field(*env->mstatus, SSTATUS_SPP));
> env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> riscv_cpu_virt_enabled(env));
> +
> + htval = env->guest_phys_fault_addr;
> }
> }
>
> @@ -922,6 +928,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
> env->sepc = env->pc;
> env->sbadaddr = tval;
> + env->htval = htval;
> env->pc = (env->stvec >> 2 << 2) +
> ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
> riscv_cpu_set_mode(env, PRV_S);
> @@ -936,6 +943,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> *env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
> riscv_cpu_force_hs_excep_enabled(env));
>
> + mtval2 = env->guest_phys_fault_addr;
> +
> /* Trapping to M mode, virt is disabled */
> riscv_cpu_set_virt_enabled(env, 0);
> }
> @@ -949,6 +958,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> env->mcause = cause | ~(((target_ulong)-1) >> async);
> env->mepc = env->pc;
> env->mbadaddr = tval;
> + env->mtval2 = mtval2;
> env->pc = (env->mtvec >> 2 << 2) +
> ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
> riscv_cpu_set_mode(env, PRV_M);
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>