Alistair Francis (8):
target/riscv: Mark privilege level 2 as reserved
target/riscv: Trigger interrupt on MIP update asynchronously
target/riscv: Improve the scause logic
target/riscv: Add the MPV and MTL mstatus bits
target/riscv: Allow setting mstatus virtulisation bits
target/riscv: Add Hypervisor CSR macros
target/riscv: Add the HSTATUS register masks
target/riscv: Add the HGATP register masks
target/riscv/cpu_bits.h | 45 +++++++++++++++++++++++++++++++++------
target/riscv/cpu_helper.c | 35 ++++++++++++++++++++++++------
target/riscv/csr.c | 19 +++++++----------
3 files changed, 74 insertions(+), 25 deletions(-)
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2.21.0