This patch series adds a generic RISC-V CPU that can be generated at run
time based on the ISA string specified to QEMU via the -cpu argument. This
is supported on the virt and spike boards allowing users to specify the
RISC-V extensions as well as the ISA version.

As part of the conversion we have deprecated the version specifi Spike
machines.

Alistair Francis (6):
  target/riscv: Fall back to generating a RISC-V CPU
  target/riscv: Create settable CPU properties
  riscv: virt: Allow specifying a CPU via commandline
  target/riscvL Remove the unused any CPU
  target/riscv: Remove the generic no MMU CPUs
  riscv: Add a generic spike machine

 hw/riscv/spike.c   | 106 ++++++++++++++++++++++++++++++++-
 hw/riscv/virt.c    |   3 +-
 target/riscv/cpu.c | 143 ++++++++++++++++++++++++++++++++++++++++++---
 target/riscv/cpu.h |  13 ++++-
 4 files changed, 251 insertions(+), 14 deletions(-)

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2.21.0