Upstream RISC-V fork patches, part 3

[Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3

Alistair Francis posted 8 patches 6 years, 9 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1547510220.git.alistair.francis@wdc.com

Maintainers: Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Riku Voipio <riku.voipio@iki.fi>, Laurent Vivier <laurent@vivier.eu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

linux-user/riscv/signal.c |   4 +-
target/riscv/cpu.c        |   2 +-
target/riscv/cpu.h        |  31 ++--
target/riscv/cpu_bits.h   |  11 ++
target/riscv/cpu_helper.c |  10 +-
target/riscv/csr.c        |  91 +++++++++---
target/riscv/fpu_helper.c |   6 +-
target/riscv/op_helper.c  |  47 ++++--
target/riscv/translate.c  | 292 ++++++++++++++++++++++++++++++++------
9 files changed, 388 insertions(+), 106 deletions(-)

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[Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3

Posted by Alistair Francis 6 years, 9 months ago

Alistair Francis (1):
  RISC-V: Add priv_ver to DisasContext

Michael Clark (5):
  RISC-V: Implement mstatus.TSR/TW/TVM
  RISC-V: Use riscv prefix consistently on cpu helpers
  RISC-V: Add misa to DisasContext
  RISC-V: Add misa.MAFD checks to translate
  RISC-V: Add misa runtime write support

Richard Henderson (2):
  RISC-V: Split out mstatus_fs from tb_flags
  RISC-V: Mark mstatus.fs dirty

 linux-user/riscv/signal.c |   4 +-
 target/riscv/cpu.c        |   2 +-
 target/riscv/cpu.h        |  31 ++--
 target/riscv/cpu_bits.h   |  11 ++
 target/riscv/cpu_helper.c |  10 +-
 target/riscv/csr.c        |  91 +++++++++---
 target/riscv/fpu_helper.c |   6 +-
 target/riscv/op_helper.c  |  47 ++++--
 target/riscv/translate.c  | 292 ++++++++++++++++++++++++++++++++------
 9 files changed, 388 insertions(+), 106 deletions(-)

-- 
2.19.1

Re: [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3

Posted by Palmer Dabbelt 6 years, 9 months ago

On Mon, 14 Jan 2019 15:57:41 PST (-0800), Alistair Francis wrote:
>
> Alistair Francis (1):
>   RISC-V: Add priv_ver to DisasContext
>
> Michael Clark (5):
>   RISC-V: Implement mstatus.TSR/TW/TVM
>   RISC-V: Use riscv prefix consistently on cpu helpers
>   RISC-V: Add misa to DisasContext
>   RISC-V: Add misa.MAFD checks to translate
>   RISC-V: Add misa runtime write support
>
> Richard Henderson (2):
>   RISC-V: Split out mstatus_fs from tb_flags
>   RISC-V: Mark mstatus.fs dirty
>
>  linux-user/riscv/signal.c |   4 +-
>  target/riscv/cpu.c        |   2 +-
>  target/riscv/cpu.h        |  31 ++--
>  target/riscv/cpu_bits.h   |  11 ++
>  target/riscv/cpu_helper.c |  10 +-
>  target/riscv/csr.c        |  91 +++++++++---
>  target/riscv/fpu_helper.c |   6 +-
>  target/riscv/op_helper.c  |  47 ++++--
>  target/riscv/translate.c  | 292 ++++++++++++++++++++++++++++++++------
>  9 files changed, 388 insertions(+), 106 deletions(-)

Thanks.  Assuming that squash is OK I'll include these in my next PR, otherwise 
just send me a v2 and I'll swap them out.