Alistair Francis (24):
  elf.h: Add the RISCV ELF magic numbers
  linux-user: Add host dependency for RISC-V 32-bit
  linux-user: Add host dependency for RISC-V 64-bit
  exec: Add RISC-V GCC poison macro
  riscv: Add the tcg-target header file
  riscv: Add the tcg target registers
  riscv: tcg-target: Add support for the constraints
  riscv: tcg-target: Add the immediate encoders
  riscv: tcg-target: Add the instruction emitters
  riscv: tcg-target: Add the relocation functions
  riscv: tcg-target: Add the mov and movi instruction
  riscv: tcg-target: Add the extract instructions
  riscv: tcg-target: Add the out load and store instructions
  riscv: tcg-target: Add branch and jump instructions
  riscv: tcg-target: Add slowpath load and store instructions
  riscv: tcg-target: Add direct load and store instructions
  riscv: tcg-target: Add the out op decoder
  riscv: tcg-target: Add the prologue generation and register the JIT
  riscv: tcg-target: Add the target init code
  tcg: Add RISC-V cpu signal handler
  dias: Add RISC-V support
  configure: Add support for building RISC-V host
  WIP: Add missing instructions
  WIP: Try to patch longer branches

 accel/tcg/user-exec.c             |   75 ++
 configure                         |   12 +-
 disas.c                           |   10 +-
 include/elf.h                     |   55 +
 include/exec/poison.h             |    1 +
 linux-user/host/riscv32/hostdep.h |   11 +
 linux-user/host/riscv64/hostdep.h |   11 +
 tcg/riscv/tcg-target.h            |  173 +++
 tcg/riscv/tcg-target.inc.c        | 1890 +++++++++++++++++++++++++++++
 9 files changed, 2234 insertions(+), 4 deletions(-)
 create mode 100644 linux-user/host/riscv32/hostdep.h
 create mode 100644 linux-user/host/riscv64/hostdep.h
 create mode 100644 tcg/riscv/tcg-target.h
 create mode 100644 tcg/riscv/tcg-target.inc.c

-- 
2.19.1

On Tue, Nov 27, 2018 at 1:06 PM Alistair Francis
<Alistair.Francis@wdc.com> wrote:

It looks like the cover was lost, here it is:

This patch set adds RISC-V backend support to QEMU. This is based on
Michael Clark's original work with some patches ontop.

This has been slightly tested and can run other architecture softmmu
code for a number of instructions but eventually QEMU will do something
it shouldn't.

I haven't tested linux user support at all yet. I think Michael had that
working reliably though and hopefully my changes haven't broken it. I'll
test both a lot more before I send a full patchset.

There are still some todos in the code (there is missing instructions
and byte swapping) and I'll have to rebase this ontop of Richard's TCG
work. In the meantime I wanted to try and keep the ball rolling though.

There are two WIP patches at the end of the series that I am not sure
about, so they have been kept seperate from the series for the time
being.

This branch can be found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend-upstream.next

The working version with Michael's orignal patch and work ontop can be
found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend.next

RFC v2:
 - A large number of changes based on Richard's feedback


>
>
> Alistair Francis (24):
>   elf.h: Add the RISCV ELF magic numbers
>   linux-user: Add host dependency for RISC-V 32-bit
>   linux-user: Add host dependency for RISC-V 64-bit
>   exec: Add RISC-V GCC poison macro
>   riscv: Add the tcg-target header file
>   riscv: Add the tcg target registers
>   riscv: tcg-target: Add support for the constraints
>   riscv: tcg-target: Add the immediate encoders
>   riscv: tcg-target: Add the instruction emitters
>   riscv: tcg-target: Add the relocation functions
>   riscv: tcg-target: Add the mov and movi instruction
>   riscv: tcg-target: Add the extract instructions
>   riscv: tcg-target: Add the out load and store instructions
>   riscv: tcg-target: Add branch and jump instructions
>   riscv: tcg-target: Add slowpath load and store instructions
>   riscv: tcg-target: Add direct load and store instructions
>   riscv: tcg-target: Add the out op decoder
>   riscv: tcg-target: Add the prologue generation and register the JIT
>   riscv: tcg-target: Add the target init code
>   tcg: Add RISC-V cpu signal handler
>   dias: Add RISC-V support
>   configure: Add support for building RISC-V host
>   WIP: Add missing instructions
>   WIP: Try to patch longer branches
>
>  accel/tcg/user-exec.c             |   75 ++
>  configure                         |   12 +-
>  disas.c                           |   10 +-
>  include/elf.h                     |   55 +
>  include/exec/poison.h             |    1 +
>  linux-user/host/riscv32/hostdep.h |   11 +
>  linux-user/host/riscv64/hostdep.h |   11 +
>  tcg/riscv/tcg-target.h            |  173 +++
>  tcg/riscv/tcg-target.inc.c        | 1890 +++++++++++++++++++++++++++++
>  9 files changed, 2234 insertions(+), 4 deletions(-)
>  create mode 100644 linux-user/host/riscv32/hostdep.h
>  create mode 100644 linux-user/host/riscv64/hostdep.h
>  create mode 100644 tcg/riscv/tcg-target.h
>  create mode 100644 tcg/riscv/tcg-target.inc.c
>
> --
> 2.19.1
>

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [RFC v2 00/24]  Add RISC-V TCG backend support
Message-id: cover.1543352682.git.alistair.francis@wdc.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
cb74f20 WIP: Try to patch longer branches
0b243f3 WIP: Add missing instructions
1a59fbe configure: Add support for building RISC-V host
e71f57d dias: Add RISC-V support
e4dea4c tcg: Add RISC-V cpu signal handler
24aab07 riscv: tcg-target: Add the target init code
1e0bb1f riscv: tcg-target: Add the prologue generation and register the JIT
5010323 riscv: tcg-target: Add the out op decoder
1aafad6 riscv: tcg-target: Add direct load and store instructions
80b4e55 riscv: tcg-target: Add slowpath load and store instructions
b4cb573 riscv: tcg-target: Add branch and jump instructions
ef58ab4 riscv: tcg-target: Add the out load and store instructions
b2ee4d7 riscv: tcg-target: Add the extract instructions
1b3b7a1 riscv: tcg-target: Add the mov and movi instruction
9836676 riscv: tcg-target: Add the relocation functions
a65fc9d riscv: tcg-target: Add the instruction emitters
73484d0 riscv: tcg-target: Add the immediate encoders
9d4b0a2 riscv: tcg-target: Add support for the constraints
70b78fc riscv: Add the tcg target registers
830a4b5 riscv: Add the tcg-target header file
049c426 exec: Add RISC-V GCC poison macro
60657c3 linux-user: Add host dependency for RISC-V 64-bit
463be15 linux-user: Add host dependency for RISC-V 32-bit
d6d6b1c elf.h: Add the RISCV ELF magic numbers

=== OUTPUT BEGIN ===
Checking PATCH 1/24: elf.h: Add the RISCV ELF magic numbers...
Checking PATCH 2/24: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 11 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/24: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 11 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/24: exec: Add RISC-V GCC poison macro...
Checking PATCH 5/24: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

WARNING: architecture specific defines should be avoided
#43: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32

total: 0 errors, 2 warnings, 173 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/24: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 116 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/24: riscv: tcg-target: Add support for the constraints...
Checking PATCH 8/24: riscv: tcg-target: Add the immediate encoders...
Checking PATCH 9/24: riscv: tcg-target: Add the instruction emitters...
Checking PATCH 10/24: riscv: tcg-target: Add the relocation functions...
Checking PATCH 11/24: riscv: tcg-target: Add the mov and movi instruction...
Checking PATCH 12/24: riscv: tcg-target: Add the extract instructions...
Checking PATCH 13/24: riscv: tcg-target: Add the out load and store instructions...
Checking PATCH 14/24: riscv: tcg-target: Add branch and jump instructions...
Checking PATCH 15/24: riscv: tcg-target: Add slowpath load and store instructions...
WARNING: line over 80 characters
#161: FILE: tcg/riscv/tcg-target.inc.c:893:
+     * see: https://lists.nongnu.org/archive/html/qemu-devel/2018-11/msg02234.html

total: 0 errors, 1 warnings, 250 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/24: riscv: tcg-target: Add direct load and store instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#87: FILE: tcg/riscv/tcg-target.inc.c:1044:
+    tcg_insn_unit *label_ptr[1];
                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#158: FILE: tcg/riscv/tcg-target.inc.c:1115:
+    tcg_insn_unit *label_ptr[1];
                   ^

total: 2 errors, 0 warnings, 178 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 17/24: riscv: tcg-target: Add the out op decoder...
Checking PATCH 18/24: riscv: tcg-target: Add the prologue generation and register the JIT...
Checking PATCH 19/24: riscv: tcg-target: Add the target init code...
Checking PATCH 20/24: tcg: Add RISC-V cpu signal handler...
Checking PATCH 21/24: dias: Add RISC-V support...
Checking PATCH 22/24: configure: Add support for building RISC-V host...
Checking PATCH 23/24: WIP: Add missing instructions...
WARNING: line over 80 characters
#62: FILE: tcg/riscv/tcg-target.inc.c:654:
+            tcg_out_opc_reg(s, OPC_SLLI, TCG_REG_TMP0, rl, (rl == bl ? al : bl));

total: 0 errors, 1 warnings, 113 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 24/24: WIP: Try to patch longer branches...
=== OUTPUT END ===

Test command exited with code: 1


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