[v1] RISC-V: Populate mtval and stval

[Qemu-devel] [PATCH v1 0/4] RISC-V: Populate mtval and stval

Alistair Francis posted 4 patches 7 years, 3 months ago

Diff against v1 v1 v2 v4
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1532559484.git.alistair.francis@wdc.com

Test docker-mingw@fedora passed

Test checkpatch passed

Test docker-quick@centos7 passed

There is a newer version of this series

target/riscv/cpu.c       |  4 ++++
target/riscv/cpu.h       |  8 +++++---
target/riscv/cpu_bits.h  |  4 ++--
target/riscv/helper.c    | 34 ++++++++++++++++++++++++++--------
target/riscv/op_helper.c | 16 ++++++++--------
target/riscv/translate.c | 12 ++++++++++++
6 files changed, 57 insertions(+), 21 deletions(-)

Expand all Fold all

[Qemu-devel] [PATCH v1 0/4] RISC-V: Populate mtval and stval

Posted by Alistair Francis 7 years, 3 months ago

Populate mtval and stval when taking an illegal instruction exception if
the features are set for the CPU.

Alistair Francis (4):
  target/riscv: Rename mbadaddr and sbadaddr
  target/riscv: Implement the mtval illegal instruction
  target/riscv: Implement the stval illegal instruction
  target/riscv: set mtval and stval support

 target/riscv/cpu.c       |  4 ++++
 target/riscv/cpu.h       |  8 +++++---
 target/riscv/cpu_bits.h  |  4 ++--
 target/riscv/helper.c    | 34 ++++++++++++++++++++++++++--------
 target/riscv/op_helper.c | 16 ++++++++--------
 target/riscv/translate.c | 12 ++++++++++++
 6 files changed, 57 insertions(+), 21 deletions(-)

-- 
2.17.1