Correct some confusion wrt. the PCI facing
side of the PCI host bridge (not PCIe root complex).
The ref. manual for the mpc8533 (as well as
mpc8540 and mpc8540) give the class code as
PCI_CLASS_PROCESSOR_POWERPC.
While the PCI_HEADER_TYPE field is oddly omitted,
the tables in the "PCI Configuration Header"
section shows a type 0 layout using all 6 BAR
registers (as 2x 32, and 2x 64 bit regions)

So 997505065dc92e533debf5cb23012ba4e673d387
seems to be in error.  Although there was
perhaps some confusion as the mpc8533
has a separate PCIe root complex.
With PCIe, a root complex has PCI_HEADER_TYPE=1.

Neither the PCI host bridge, nor the PCIe
root complex advertise class PCI_CLASS_BRIDGE_PCI.

This was confusing Linux guests, which try
to interpret the host bridge as a pci-pci
bridge, but get confused and re-enumerate
the bus when the primary/secondary/subordinate
bus registers don't have valid values.

Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
---
 hw/pci-host/ppce500.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index f2d108bc8a..8073d396ff 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -423,11 +423,6 @@ static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
                                                       "/e500-ccsr"));
     MemoryRegion *ccsr_mr = sysbus_mmio_get_region(ccsr, 0);
 
-    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
-    d->config[PCI_HEADER_TYPE] =
-        (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
-        PCI_HEADER_TYPE_BRIDGE;
-
     memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", ccsr_mr,
                              0, memory_region_size(ccsr_mr));
     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
-- 
2.11.0

On Sun, Nov 26, 2017 at 03:59:05PM -0600, Michael Davidsaver wrote:
> Correct some confusion wrt. the PCI facing
> side of the PCI host bridge (not PCIe root complex).
> The ref. manual for the mpc8533 (as well as
> mpc8540 and mpc8540) give the class code as
> PCI_CLASS_PROCESSOR_POWERPC.
> While the PCI_HEADER_TYPE field is oddly omitted,
> the tables in the "PCI Configuration Header"
> section shows a type 0 layout using all 6 BAR
> registers (as 2x 32, and 2x 64 bit regions)
> 
> So 997505065dc92e533debf5cb23012ba4e673d387
> seems to be in error.  Although there was
> perhaps some confusion as the mpc8533
> has a separate PCIe root complex.
> With PCIe, a root complex has PCI_HEADER_TYPE=1.
> 
> Neither the PCI host bridge, nor the PCIe
> root complex advertise class PCI_CLASS_BRIDGE_PCI.
> 
> This was confusing Linux guests, which try
> to interpret the host bridge as a pci-pci
> bridge, but get confused and re-enumerate
> the bus when the primary/secondary/subordinate
> bus registers don't have valid values.
> 
> Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>

Applied to ppc-for-2.12.

> ---
>  hw/pci-host/ppce500.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
> index f2d108bc8a..8073d396ff 100644
> --- a/hw/pci-host/ppce500.c
> +++ b/hw/pci-host/ppce500.c
> @@ -423,11 +423,6 @@ static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
>                                                        "/e500-ccsr"));
>      MemoryRegion *ccsr_mr = sysbus_mmio_get_region(ccsr, 0);
>  
> -    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
> -    d->config[PCI_HEADER_TYPE] =
> -        (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
> -        PCI_HEADER_TYPE_BRIDGE;
> -
>      memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", ccsr_mr,
>                               0, memory_region_size(ccsr_mr));
>      pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson