This series adds the ZynqMP Power Management Unit (PMU) machine with basic
functionality.

The machine only has the
 - CPU
 - Memory
 - Interrupt controller
 - IPI device

connected, but that is enough to run some of the ROM and firmware
code on the machine

The series also adds the IPI device and connects it to the ZynqMP ARM
side and the ZynqMP PMU. These IPI devices don't connect between the ARM
and MicroBlaze instances though.

v3:
 - Add the interrupt controller
 - Replace some of the error_fatals with errp
 - Fix the PMU CPU name



Alistair Francis (8):
  xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU
  xlnx-zynqmp-pmu: Add the CPU and memory
  aarch64-softmmu.mak: Use an ARM specific config
  xlnx-pmu-iomod-intc: Add the PMU Interrupt controller
  xlnx-zynqmp-pmu: Connect the PMU interrupt controller
  xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device
  xlnx-zynqmp-pmu: Connect the IPI device to the PMU
  xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC

 default-configs/aarch64-softmmu.mak    |   1 +
 default-configs/microblaze-softmmu.mak |   1 +
 hw/arm/Makefile.objs                   |   2 +-
 hw/arm/xlnx-zynqmp.c                   |  14 +
 hw/display/Makefile.objs               |   2 +-
 hw/dma/Makefile.objs                   |   2 +-
 hw/intc/Makefile.objs                  |   2 +
 hw/intc/xlnx-pmu-iomod-intc.c          | 554 +++++++++++++++++++++++++++++++++
 hw/intc/xlnx-zynqmp-ipi.c              | 377 ++++++++++++++++++++++
 hw/microblaze/Makefile.objs            |   1 +
 hw/microblaze/xlnx-zynqmp-pmu.c        | 200 ++++++++++++
 include/hw/arm/xlnx-zynqmp.h           |   2 +
 include/hw/intc/xlnx-pmu-iomod-intc.h  |  58 ++++
 include/hw/intc/xlnx-zynqmp-ipi.h      |  57 ++++
 14 files changed, 1270 insertions(+), 3 deletions(-)
 create mode 100644 hw/intc/xlnx-pmu-iomod-intc.c
 create mode 100644 hw/intc/xlnx-zynqmp-ipi.c
 create mode 100644 hw/microblaze/xlnx-zynqmp-pmu.c
 create mode 100644 include/hw/intc/xlnx-pmu-iomod-intc.h
 create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h

-- 
2.11.0

On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote:
> 
> This series adds the ZynqMP Power Management Unit (PMU) machine with basic
> functionality.
> 
> The machine only has the
>  - CPU
>  - Memory
>  - Interrupt controller
>  - IPI device
> 
> connected, but that is enough to run some of the ROM and firmware
> code on the machine
> 
> The series also adds the IPI device and connects it to the ZynqMP ARM
> side and the ZynqMP PMU. These IPI devices don't connect between the ARM
> and MicroBlaze instances though.
> 
> v3:
>  - Add the interrupt controller
>  - Replace some of the error_fatals with errp
>  - Fix the PMU CPU name

Hi Alistair,


Sorry for the super long delay...

I think this mostly looks good but I was wondering if we really need
to have a board specific (zcu102) PMU?

Best regards,
Edgar



> 
> 
> 
> Alistair Francis (8):
>   xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU
>   xlnx-zynqmp-pmu: Add the CPU and memory
>   aarch64-softmmu.mak: Use an ARM specific config
>   xlnx-pmu-iomod-intc: Add the PMU Interrupt controller
>   xlnx-zynqmp-pmu: Connect the PMU interrupt controller
>   xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device
>   xlnx-zynqmp-pmu: Connect the IPI device to the PMU
>   xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC
> 
>  default-configs/aarch64-softmmu.mak    |   1 +
>  default-configs/microblaze-softmmu.mak |   1 +
>  hw/arm/Makefile.objs                   |   2 +-
>  hw/arm/xlnx-zynqmp.c                   |  14 +
>  hw/display/Makefile.objs               |   2 +-
>  hw/dma/Makefile.objs                   |   2 +-
>  hw/intc/Makefile.objs                  |   2 +
>  hw/intc/xlnx-pmu-iomod-intc.c          | 554 +++++++++++++++++++++++++++++++++
>  hw/intc/xlnx-zynqmp-ipi.c              | 377 ++++++++++++++++++++++
>  hw/microblaze/Makefile.objs            |   1 +
>  hw/microblaze/xlnx-zynqmp-pmu.c        | 200 ++++++++++++
>  include/hw/arm/xlnx-zynqmp.h           |   2 +
>  include/hw/intc/xlnx-pmu-iomod-intc.h  |  58 ++++
>  include/hw/intc/xlnx-zynqmp-ipi.h      |  57 ++++
>  14 files changed, 1270 insertions(+), 3 deletions(-)
>  create mode 100644 hw/intc/xlnx-pmu-iomod-intc.c
>  create mode 100644 hw/intc/xlnx-zynqmp-ipi.c
>  create mode 100644 hw/microblaze/xlnx-zynqmp-pmu.c
>  create mode 100644 include/hw/intc/xlnx-pmu-iomod-intc.h
>  create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h
> 
> -- 
> 2.11.0
> 

On Sun, Oct 8, 2017 at 3:20 PM, Edgar E. Iglesias
<edgar.iglesias@xilinx.com> wrote:
> On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote:
>>
>> This series adds the ZynqMP Power Management Unit (PMU) machine with basic
>> functionality.
>>
>> The machine only has the
>>  - CPU
>>  - Memory
>>  - Interrupt controller
>>  - IPI device
>>
>> connected, but that is enough to run some of the ROM and firmware
>> code on the machine
>>
>> The series also adds the IPI device and connects it to the ZynqMP ARM
>> side and the ZynqMP PMU. These IPI devices don't connect between the ARM
>> and MicroBlaze instances though.
>>
>> v3:
>>  - Add the interrupt controller
>>  - Replace some of the error_fatals with errp
>>  - Fix the PMU CPU name
>
> Hi Alistair,
>
>
> Sorry for the super long delay...
>
> I think this mostly looks good but I was wondering if we really need
> to have a board specific (zcu102) PMU?

It doesn't have to be board specific. What I wanted though was an SoC
and a machine so that maybe one day we could add the PMU SoC to the
ARM ZCU102 machine. After that it was hard to think of a name to
differentiate the SoC and the machine. Do you have a recommendation on
names?

Thanks,
Alistair

>
> Best regards,
> Edgar
>
>
>
>>
>>
>>
>> Alistair Francis (8):
>>   xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU
>>   xlnx-zynqmp-pmu: Add the CPU and memory
>>   aarch64-softmmu.mak: Use an ARM specific config
>>   xlnx-pmu-iomod-intc: Add the PMU Interrupt controller
>>   xlnx-zynqmp-pmu: Connect the PMU interrupt controller
>>   xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device
>>   xlnx-zynqmp-pmu: Connect the IPI device to the PMU
>>   xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC
>>
>>  default-configs/aarch64-softmmu.mak    |   1 +
>>  default-configs/microblaze-softmmu.mak |   1 +
>>  hw/arm/Makefile.objs                   |   2 +-
>>  hw/arm/xlnx-zynqmp.c                   |  14 +
>>  hw/display/Makefile.objs               |   2 +-
>>  hw/dma/Makefile.objs                   |   2 +-
>>  hw/intc/Makefile.objs                  |   2 +
>>  hw/intc/xlnx-pmu-iomod-intc.c          | 554 +++++++++++++++++++++++++++++++++
>>  hw/intc/xlnx-zynqmp-ipi.c              | 377 ++++++++++++++++++++++
>>  hw/microblaze/Makefile.objs            |   1 +
>>  hw/microblaze/xlnx-zynqmp-pmu.c        | 200 ++++++++++++
>>  include/hw/arm/xlnx-zynqmp.h           |   2 +
>>  include/hw/intc/xlnx-pmu-iomod-intc.h  |  58 ++++
>>  include/hw/intc/xlnx-zynqmp-ipi.h      |  57 ++++
>>  14 files changed, 1270 insertions(+), 3 deletions(-)
>>  create mode 100644 hw/intc/xlnx-pmu-iomod-intc.c
>>  create mode 100644 hw/intc/xlnx-zynqmp-ipi.c
>>  create mode 100644 hw/microblaze/xlnx-zynqmp-pmu.c
>>  create mode 100644 include/hw/intc/xlnx-pmu-iomod-intc.h
>>  create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h
>>
>> --
>> 2.11.0
>>

On Mon, Oct 09, 2017 at 05:12:39PM -0700, Alistair Francis wrote:
> On Sun, Oct 8, 2017 at 3:20 PM, Edgar E. Iglesias
> <edgar.iglesias@xilinx.com> wrote:
> > On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote:
> >>
> >> This series adds the ZynqMP Power Management Unit (PMU) machine with basic
> >> functionality.
> >>
> >> The machine only has the
> >>  - CPU
> >>  - Memory
> >>  - Interrupt controller
> >>  - IPI device
> >>
> >> connected, but that is enough to run some of the ROM and firmware
> >> code on the machine
> >>
> >> The series also adds the IPI device and connects it to the ZynqMP ARM
> >> side and the ZynqMP PMU. These IPI devices don't connect between the ARM
> >> and MicroBlaze instances though.
> >>
> >> v3:
> >>  - Add the interrupt controller
> >>  - Replace some of the error_fatals with errp
> >>  - Fix the PMU CPU name
> >
> > Hi Alistair,
> >
> >
> > Sorry for the super long delay...
> >
> > I think this mostly looks good but I was wondering if we really need
> > to have a board specific (zcu102) PMU?
> 
> It doesn't have to be board specific. What I wanted though was an SoC
> and a machine so that maybe one day we could add the PMU SoC to the
> ARM ZCU102 machine. After that it was hard to think of a name to
> differentiate the SoC and the machine. Do you have a recommendation on
> names?


Hi Alistair,

Yes, I agree with your approach but I got a little confused by the names.

I think all the stuff that is inside the PMU subsystem architecture-wise
should have generic PMU names (no ZCU102). I.e the ROM, the RAM, the IOModule,
interrupt controller etc.

The IPI block can be outside of the PMU module and be instantiated by the
board or perhaps better if we could reuse some of the ZynqMP modules
instantiated by the ZCU102 machine to get a CPU-less PS for the PMU
to interact with. Or something along those lines.
How does that sound?

Best regards,
Edgar

On Tue, Oct 10, 2017 at 7:48 AM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Mon, Oct 09, 2017 at 05:12:39PM -0700, Alistair Francis wrote:
>> On Sun, Oct 8, 2017 at 3:20 PM, Edgar E. Iglesias
>> <edgar.iglesias@xilinx.com> wrote:
>> > On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote:
>> >>
>> >> This series adds the ZynqMP Power Management Unit (PMU) machine with basic
>> >> functionality.
>> >>
>> >> The machine only has the
>> >>  - CPU
>> >>  - Memory
>> >>  - Interrupt controller
>> >>  - IPI device
>> >>
>> >> connected, but that is enough to run some of the ROM and firmware
>> >> code on the machine
>> >>
>> >> The series also adds the IPI device and connects it to the ZynqMP ARM
>> >> side and the ZynqMP PMU. These IPI devices don't connect between the ARM
>> >> and MicroBlaze instances though.
>> >>
>> >> v3:
>> >>  - Add the interrupt controller
>> >>  - Replace some of the error_fatals with errp
>> >>  - Fix the PMU CPU name
>> >
>> > Hi Alistair,
>> >
>> >
>> > Sorry for the super long delay...
>> >
>> > I think this mostly looks good but I was wondering if we really need
>> > to have a board specific (zcu102) PMU?
>>
>> It doesn't have to be board specific. What I wanted though was an SoC
>> and a machine so that maybe one day we could add the PMU SoC to the
>> ARM ZCU102 machine. After that it was hard to think of a name to
>> differentiate the SoC and the machine. Do you have a recommendation on
>> names?
>
>
> Hi Alistair,
>
> Yes, I agree with your approach but I got a little confused by the names.
>
> I think all the stuff that is inside the PMU subsystem architecture-wise
> should have generic PMU names (no ZCU102). I.e the ROM, the RAM, the IOModule,
> interrupt controller etc.

Ok I can rename them to the ZynqMP PMU (the machine/board) and the
ZynqMP PMU SoC. Does that work?

>
> The IPI block can be outside of the PMU module and be instantiated by the
> board or perhaps better if we could reuse some of the ZynqMP modules
> instantiated by the ZCU102 machine to get a CPU-less PS for the PMU
> to interact with. Or something along those lines.
> How does that sound?>

I'm a little unclear what you mean here.

Thanks,
Alistair

> Best regards,
> Edgar
>

On Oct 10, 2017 7:59 PM, "Alistair Francis" <alistair.francis@xilinx.com>
wrote:

On Tue, Oct 10, 2017 at 7:48 AM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Mon, Oct 09, 2017 at 05:12:39PM -0700, Alistair Francis wrote:
>> On Sun, Oct 8, 2017 at 3:20 PM, Edgar E. Iglesias
>> <edgar.iglesias@xilinx.com> wrote:
>> > On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote:
>> >>
>> >> This series adds the ZynqMP Power Management Unit (PMU) machine with
basic
>> >> functionality.
>> >>
>> >> The machine only has the
>> >>  - CPU
>> >>  - Memory
>> >>  - Interrupt controller
>> >>  - IPI device
>> >>
>> >> connected, but that is enough to run some of the ROM and firmware
>> >> code on the machine
>> >>
>> >> The series also adds the IPI device and connects it to the ZynqMP ARM
>> >> side and the ZynqMP PMU. These IPI devices don't connect between the
ARM
>> >> and MicroBlaze instances though.
>> >>
>> >> v3:
>> >>  - Add the interrupt controller
>> >>  - Replace some of the error_fatals with errp
>> >>  - Fix the PMU CPU name
>> >
>> > Hi Alistair,
>> >
>> >
>> > Sorry for the super long delay...
>> >
>> > I think this mostly looks good but I was wondering if we really need
>> > to have a board specific (zcu102) PMU?
>>
>> It doesn't have to be board specific. What I wanted though was an SoC
>> and a machine so that maybe one day we could add the PMU SoC to the
>> ARM ZCU102 machine. After that it was hard to think of a name to
>> differentiate the SoC and the machine. Do you have a recommendation on
>> names?
>
>
> Hi Alistair,
>
> Yes, I agree with your approach but I got a little confused by the names.
>
> I think all the stuff that is inside the PMU subsystem architecture-wise
> should have generic PMU names (no ZCU102). I.e the ROM, the RAM, the
IOModule,
> interrupt controller etc.

Ok I can rename them to the ZynqMP PMU (the machine/board) and the
ZynqMP PMU SoC. Does that work?

>
> The IPI block can be outside of the PMU module and be instantiated by the
> board or perhaps better if we could reuse some of the ZynqMP modules
> instantiated by the ZCU102 machine to get a CPU-less PS for the PMU
> to interact with. Or something along those lines.
> How does that sound?>

I'm a little unclear what you mean here.

Thanks,
Alistair

> Best regards,
> Edgar
>


Hi Alistair,

To clarify, if you create a pmu object, try to only put stuff in that
object that belong to the pmu subsystem. The IPI block for example doesn't,
it belongs outside of the pmu object allthough you will want to instate an
ipi instance in the pmu machine.

Hope that helps
Edgar

Sent from my phone