linux-user/riscv: fix zicntr gating and reservations

[PATCH v2 0/2] linux-user/riscv: fix zicntr gating and reservations

wangyang posted 2 patches 2 weeks, 1 day ago

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Failed in applying to current master (apply log)

linux-user/riscv/target_cpu.h                 |  2 +
target/riscv/cpu.c                            |  3 ++
target/riscv/cpu.h                            |  3 ++
target/riscv/helper.h                         |  5 +++
target/riscv/tcg/csr.c                        | 11 ++++--
target/riscv/tcg/insn_trans/trans_rva.c.inc   | 24 ++++++++++++
target/riscv/tcg/insn_trans/trans_rvi.c.inc   | 11 ++++++
.../riscv/tcg/insn_trans/trans_rvzawrs.c.inc  |  3 ++
target/riscv/tcg/op_helper.c                  | 35 +++++++++++++++++
target/riscv/tcg/translate.c                  | 38 +++++++++++++++++++
10 files changed, 131 insertions(+), 4 deletions(-)

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[PATCH v2 0/2] linux-user/riscv: fix zicntr gating and reservations

Posted by wangyang 2 weeks, 1 day ago

This is a refreshed two-patch series for the linux-user/RISC-V issues
tracked by Work Items #4148 and #4149. The patches address independent
defects in the same subsystem and are sent together for review.

Patch 1 fixes the linux-user Zicntr extension gate. Patch 2 fixes
reservation invalidation for base scalar integer stores and
A-extension AMOs.
Patch 2 also clears reservation state when a new linux-user RISC-V hart
is cloned, and uses QEMU's existing EXCP_ATOMIC path to linearize the
completed memory operation with reservation invalidation.

Changes since v1:
- Rebased the series onto current master.
- Added a cover letter and resent the complete two-patch series.
- Expanded patch 2 to cover ordinary scalar integer stores as well as
  AMOs.
- Recorded the LR access range and handled reservation state across hart
  cloning.
- Patch 2 changed materially, so it requests a fresh review.

Thank you for the review guidance. This version follows the series
structure and includes the missing cover letter. Please accept my
apologies for overlooking those community requirements.

Testing:
- The 14-case RV64 linux-user witness covers same-value stores,
  preserve-value AMOs, word/doubleword operations, overlapping addresses,
  distant-address controls, and two guest harts.
- The current-master baseline reports 12 required failures; the fixed
  build reports 14 cases and 0 failures.
- A supplementary clone witness reports child SC failure and unchanged
  memory on the fixed build.
- The Zicntr witness reports SIGILL for all three disabled base counters
  and retains the enabled-extension control behavior.

Existing Work Items:
- https://gitlab.com/qemu-project/qemu/-/work_items/4148
- https://gitlab.com/qemu-project/qemu/-/work_items/4149

wangyang (2):
  linux-user/riscv: honor zicntr=false for base counter CSRs
  linux-user/riscv: invalidate reservations after stores

 linux-user/riscv/target_cpu.h                 |  2 +
 target/riscv/cpu.c                            |  3 ++
 target/riscv/cpu.h                            |  3 ++
 target/riscv/helper.h                         |  5 +++
 target/riscv/tcg/csr.c                        | 11 ++++--
 target/riscv/tcg/insn_trans/trans_rva.c.inc   | 24 ++++++++++++
 target/riscv/tcg/insn_trans/trans_rvi.c.inc   | 11 ++++++
 .../riscv/tcg/insn_trans/trans_rvzawrs.c.inc  |  3 ++
 target/riscv/tcg/op_helper.c                  | 35 +++++++++++++++++
 target/riscv/tcg/translate.c                  | 38 +++++++++++++++++++
 10 files changed, 131 insertions(+), 4 deletions(-)