Hi Philippe, Cédric
> Subject: Re: [PATCH v2 0/8] Refactor AST2700 SCU preparation for coprocessors
>
> On 7/7/26 08:09, Jamin Lin wrote:
> > The original AST2700 FC support series [1] is fairly large, making it
> > difficult to review all changes together.
> >
> > To help speed up the review process, this series extracts the
> > SCU/FMC-related refactoring into a standalone prerequisite series.
>
>
> > hw/arm/aspeed_ast27x0-ssp.c | 56 +++++++++++---
> > hw/arm/aspeed_ast27x0-tsp.c | 56 +++++++++++---
> > hw/arm/aspeed_coprocessor_common.c | 2 -
>
> It is unfortunate these 2 complex models diverge so few...
>
> $ diff -u -U0 hw/arm/aspeed_ast27x0-tsp.c hw/arm/aspeed_ast27x0-ssp.c
> --- hw/arm/aspeed_ast27x0-tsp.c 2026-07-09 18:42:33
> +++ hw/arm/aspeed_ast27x0-ssp.c 2026-07-09 18:42:33
> @@ -2 +2 @@
> - * ASPEED Ast27x0 TSP Coprocessor
> + * ASPEED Ast27x0 SSP Coprocessor
> @@ -19 +19 @@
> -#define AST2700_TSP_SDRAM_SIZE (512 * MiB)
> +#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
> @@ -21 +21 @@
> -static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
> +static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> @@ -50 +50 @@
> -static const int aspeed_soc_ast27x0tsp_irqmap[] = {
> +static const int aspeed_soc_ast27x0ssp_irqmap[] = {
> @@ -68,2 +68,2 @@
> -/* TSPINT 164 */
> -static const int ast2700_tsp164_intcmap[] = {
> +/* SSPINT 164 */
> +static const int ast2700_ssp164_intcmap[] = {
> @@ -91 +91 @@
> -static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
> +static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
> @@ -96 +96 @@
> - {164, 1, 4, ast2700_tsp164_intcmap},
> + {164, 1, 4, ast2700_ssp164_intcmap},
> @@ -104 +104 @@
> -static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s,
> +static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState
> +*s,
> @@ -107 +107 @@
> - Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(s);
> + Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(s);
> @@ -114,5 +114,5 @@
> - for (i = 0; i < ARRAY_SIZE(ast2700_tsp_intcmap); i++) {
> - if (sc->irqmap[dev] == ast2700_tsp_intcmap[i].irq) {
> - assert(ast2700_tsp_intcmap[i].ptr);
> - or_idx = ast2700_tsp_intcmap[i].orgate_idx;
> - idx = ast2700_tsp_intcmap[i].intc_idx;
> + for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
> + if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
> + assert(ast2700_ssp_intcmap[i].ptr);
> + or_idx = ast2700_ssp_intcmap[i].orgate_idx;
> + idx = ast2700_ssp_intcmap[i].intc_idx;
> @@ -120 +120 @@
> - ast2700_tsp_intcmap[i].ptr[dev]);
> +
> ast2700_ssp_intcmap[i].ptr[dev]);
> @@ -127 +127 @@
> -static void aspeed_soc_ast27x0tsp_init(Object *obj)
> +static void aspeed_soc_ast27x0ssp_init(Object *obj)
> @@ -129 +129 @@
> - Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(obj);
> + Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(obj);
> @@ -136 +136 @@
> - TYPE_ASPEED_2700TSP_INTC);
> + TYPE_ASPEED_2700SSP_INTC);
> @@ -138 +138 @@
> - TYPE_ASPEED_2700TSP_INTCIO);
> + TYPE_ASPEED_2700SSP_INTCIO);
> @@ -154 +154 @@
> -static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error
> **errp)
> +static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error
> **errp)
> @@ -156 +156 @@
> - Aspeed27x0CoprocessorState *a =
> ASPEED27X0TSP_COPROCESSOR(dev_soc);
> + Aspeed27x0CoprocessorState *a =
> ASPEED27X0SSP_COPROCESSOR(dev_soc);
> @@ -170 +170 @@
> - error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
> + error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
> @@ -176 +176 @@
> - error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
> + error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
> @@ -182 +182 @@
> - error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
> + error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
> @@ -187 +187 @@
> - /* AST27X0 TSP Core */
> + /* AST27X0 SSP Core */
> @@ -196,2 +196,2 @@
> - * The TSP starts in a powered-down state and can be powered up
> - * by setting the TSP Control Register through the SCU
> + * The SSP starts in a powered-down state and can be powered up
> + * by setting the SSP Control Register through the SCU
> @@ -208 +208 @@
> - AST2700_TSP_SDRAM_SIZE, errp)) {
> + AST2700_SSP_SDRAM_SIZE, errp)) {
> @@ -235,2 +235,5 @@
> - /* SDRAM remap alias used by PSP to access TSP SDRAM */
> - memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[2]);
> + /* SDRAM remap alias used by PSP to access SSP SDRAM */
> + memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[1]);
> + memory_region_add_subregion(&s->sdram,
> + memory_region_size(&a->scu->dram_remap_alias[1]),
> + &a->scu->dram_remap_alias[0]);
> @@ -254 +257 @@
> - /* irq source orgates -> INTC */
> + /* irq source orgates -> INTC0 */
> @@ -260 +263 @@
> - assert(i < ARRAY_SIZE(ast2700_tsp_intcmap));
> + assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
> @@ -263 +266 @@
> -
> ast2700_tsp_intcmap[i].irq));
> +
> + ast2700_ssp_intcmap[i].irq));
> @@ -265 +268 @@
> - /* irq source orgates -> INTC */
> + /* irq source orgates -> INTCIO */
> @@ -287 +290 @@
> - aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
> + aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
> @@ -325 +328 @@
> -static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
> +static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
> @@ -329 +332 @@
> - ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
> + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
> @@ -337 +340 @@
> - dc->realize = aspeed_soc_ast27x0tsp_realize;
> + dc->realize = aspeed_soc_ast27x0ssp_realize;
> @@ -341,2 +344,2 @@
> - sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
> - sc->memmap = aspeed_soc_ast27x0tsp_memmap;
> + sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
> + sc->memmap = aspeed_soc_ast27x0ssp_memmap;
> @@ -345 +348 @@
> -static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
> +static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
> @@ -347 +350 @@
> - .name = TYPE_ASPEED27X0TSP_COPROCESSOR,
> + .name = TYPE_ASPEED27X0SSP_COPROCESSOR,
> @@ -350,2 +353,2 @@
> - .instance_init = aspeed_soc_ast27x0tsp_init,
> - .class_init = aspeed_soc_ast27x0tsp_class_init,
> + .instance_init = aspeed_soc_ast27x0ssp_init,
> + .class_init = aspeed_soc_ast27x0ssp_class_init,
> @@ -355 +358 @@
> -DEFINE_TYPES(aspeed_soc_ast27x0tsp_types)
> +DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
>
> And without the s/tsp/ssp/ name changes, the diff is as small as:
>
> $ diff -u -U0 hw/arm/aspeed_ast27x0-tsp.c hw/arm/aspeed_ast27x0-ssp.c
> --- hw/arm/aspeed_ast27x0-tsp.c 2026-07-09 18:42:33
> +++ hw/arm/aspeed_ast27x0-ssp.c 2026-07-10 01:10:06
> @@ -236 +236,4 @@
> - memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[2]);
> + memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[1]);
> + memory_region_add_subregion(&s->sdram,
> + memory_region_size(&a->scu->dram_remap_alias[1]),
> + &a->scu->dram_remap_alias[0]);
>
> 2 lines of differences! Could we unify?
>
> Thanks,
>
> Phil.
Below is my initial revision — please evaluate whether it needs to be merged into a single .c file.
The SSP and TSP coprocessor files are now identical except for two things, both stemming from the fact that SSP and TSP share the same PSP SCU instance:
- INTC/INTCIO subtype (TYPE_ASPEED_2700SSP_INTC vs TYPE_ASPEED_2700TSP_INTC)
- DRAM remap alias wiring — the SCU owns a single dram_remap_alias[] array shared by both cores (SSP uses two entries, TSP uses one), so each coprocessor needs to know which slice belongs to it.
Thanks,
Jamin
/*
* ASPEED Ast27x0 SSP/TSP Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/core/qdev-clock.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_coprocessor.h"
#define AST2700_COPROCESSOR_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0_coprocessor_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_PRIC0] = 0x72140000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
[ASPEED_DEV_UART4] = 0x72C1A000,
[ASPEED_DEV_IPC0] = 0x72C1C000,
[ASPEED_DEV_FMC] = 0x74000000,
[ASPEED_DEV_PRIC1] = 0x74100000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
[ASPEED_DEV_OTP] = 0x74C07000,
[ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
[ASPEED_DEV_UART1] = 0x74C33100,
[ASPEED_DEV_UART2] = 0x74C33200,
[ASPEED_DEV_UART3] = 0x74C33300,
[ASPEED_DEV_UART5] = 0x74C33400,
[ASPEED_DEV_UART6] = 0x74C33500,
[ASPEED_DEV_UART7] = 0x74C33600,
[ASPEED_DEV_UART8] = 0x74C33700,
[ASPEED_DEV_UART9] = 0x74C33800,
[ASPEED_DEV_UART10] = 0x74C33900,
[ASPEED_DEV_UART11] = 0x74C33A00,
[ASPEED_DEV_UART12] = 0x74C33B00,
[ASPEED_DEV_IPC1] = 0x74C39000,
};
static const int aspeed_soc_ast27x0_coprocessor_irqmap[] = {
[ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_SCU] = 12,
[ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_UART0] = 164,
[ASPEED_DEV_UART1] = 164,
[ASPEED_DEV_UART2] = 164,
[ASPEED_DEV_UART3] = 164,
[ASPEED_DEV_UART5] = 164,
[ASPEED_DEV_UART6] = 164,
[ASPEED_DEV_UART7] = 164,
[ASPEED_DEV_UART8] = 164,
[ASPEED_DEV_UART9] = 164,
[ASPEED_DEV_UART10] = 164,
[ASPEED_DEV_UART11] = 164,
[ASPEED_DEV_UART12] = 164,
};
/* IRQ 164 fans out to per-UART interrupts inside the shared orgate */
static const int ast2700_coprocessor_164_intcmap[] = {
[ASPEED_DEV_UART0] = 7,
[ASPEED_DEV_UART1] = 8,
[ASPEED_DEV_UART2] = 9,
[ASPEED_DEV_UART3] = 10,
[ASPEED_DEV_UART5] = 11,
[ASPEED_DEV_UART6] = 12,
[ASPEED_DEV_UART7] = 13,
[ASPEED_DEV_UART8] = 14,
[ASPEED_DEV_UART9] = 15,
[ASPEED_DEV_UART10] = 16,
[ASPEED_DEV_UART11] = 17,
[ASPEED_DEV_UART12] = 18,
};
struct nvic_intc_irq_info {
int irq;
int intc_idx;
int orgate_idx;
const int *ptr;
};
static struct nvic_intc_irq_info ast2700_coprocessor_intcmap[] = {
{160, 1, 0, NULL},
{161, 1, 1, NULL},
{162, 1, 2, NULL},
{163, 1, 3, NULL},
{164, 1, 4, ast2700_coprocessor_164_intcmap},
{165, 1, 5, NULL},
{166, 1, 6, NULL},
{167, 1, 7, NULL},
{168, 1, 8, NULL},
{169, 1, 9, NULL},
};
static MemoryRegion *ast27x0ssp_dram_remap_alias(Aspeed2700SCUState *scu,
int *n)
{
*n = ARRAY_SIZE(scu->ssp_dram_remap_alias);
return scu->ssp_dram_remap_alias;
}
static MemoryRegion *ast27x0tsp_dram_remap_alias(Aspeed2700SCUState *scu,
int *n)
{
*n = ARRAY_SIZE(scu->tsp_dram_remap_alias);
return scu->tsp_dram_remap_alias;
}
static qemu_irq aspeed_soc_ast27x0_coprocessor_get_irq(AspeedCoprocessorState *s,
int dev)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0_COPROCESSOR(s);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
int idx;
int i;
for (i = 0; i < ARRAY_SIZE(ast2700_coprocessor_intcmap); i++) {
if (sc->irqmap[dev] == ast2700_coprocessor_intcmap[i].irq) {
assert(ast2700_coprocessor_intcmap[i].ptr);
or_idx = ast2700_coprocessor_intcmap[i].orgate_idx;
idx = ast2700_coprocessor_intcmap[i].intc_idx;
return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
ast2700_coprocessor_intcmap[i].ptr[dev]);
}
}
return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
}
static void aspeed_soc_ast27x0_coprocessor_init(Object *obj)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0_COPROCESSOR(obj);
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_GET_CLASS(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
object_initialize_child(obj, "intc0", &a->intc[0], c->intc_type);
object_initialize_child(obj, "intc1", &a->intc[1], c->intcio_type);
object_initialize_child(obj, "timerctrl", &s->timerctrl,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ipc0", &a->ipc[0],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ipc1", &a->ipc[1],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric0", &a->pric[0],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric1", &a->pric[1],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "otp", &a->otp,
TYPE_UNIMPLEMENTED_DEVICE);
}
static void aspeed_soc_ast27x0_coprocessor_realize(DeviceState *dev_soc,
Error **errp)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0_COPROCESSOR(dev_soc);
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_GET_CLASS(dev_soc);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
MemoryRegion *mr;
MemoryRegion *remaps;
g_autofree char *sdram_name = NULL;
hwaddr remap_off;
int n;
int i;
if (!clock_has_source(s->sysclk)) {
error_setg(errp, "sysclk clock must be wired up by the board code");
return;
}
if (!a->scu) {
error_setg(errp, "%s: 'scu' link is not set",
object_get_typename(OBJECT(dev_soc)));
return;
}
if (!a->scuio) {
error_setg(errp, "%s: 'scuio' link is not set",
object_get_typename(OBJECT(dev_soc)));
return;
}
if (!a->fmc) {
error_setg(errp, "%s: 'fmc' link is not set",
object_get_typename(OBJECT(dev_soc)));
return;
}
/* AST27X0 SSP/TSP Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
qdev_prop_set_string(armv7m, "cpu-type",
aspeed_soc_cpu_type(sc->valid_cpu_types));
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
/*
* The coprocessor starts in a powered-down state and can be powered up
* by setting its Control Register through the SCU (System Control Unit)
*/
object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
sdram_name = g_strdup_printf("aspeed.sdram.%d",
CPU(a->armv7m.cpu)->cpu_index);
if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
AST2700_COPROCESSOR_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SDRAM],
&s->sdram);
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
memory_region_init_alias(&a->scu_alias, OBJECT(a), "scu.alias",
&a->scu->parent_obj.iomem, 0,
memory_region_size(&a->scu->parent_obj.iomem));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&a->scu_alias);
/* SCUIO */
memory_region_init_alias(&a->scuio_alias, OBJECT(a), "scuio.alias",
&a->scuio->iomem, 0,
memory_region_size(&a->scuio->iomem));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
&a->scuio_alias);
/*
* SDRAM remap alias used by PSP to access this coprocessor's SDRAM.
* Which/how many dram_remap_alias entries to concatenate is a per-model
* detail (see Aspeed27x0CoprocessorClass): SSP maps two, TSP maps one.
*/
remaps = c->dram_remap_alias(a->scu, &n);
remap_off = 0;
for (i = 0; i < n; i++) {
memory_region_add_subregion(&s->sdram, remap_off, &remaps[i]);
remap_off += memory_region_size(&remaps[i]);
}
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC]);
/* INTCIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
return;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
sc->memmap[ASPEED_DEV_INTCIO]);
/* irq source orgates -> INTC0 */
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
}
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
assert(i < ARRAY_SIZE(ast2700_coprocessor_intcmap));
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
qdev_get_gpio_in(DEVICE(&a->armv7m),
ast2700_coprocessor_intcmap[i].irq));
}
/* irq source orgates -> INTCIO */
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
}
/* INTCIO -> INTC */
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(s->uart), 0);
memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias", mr, 0,
memory_region_size(mr));
memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
&s->uart_alias);
/*
* Redirect the UART interrupt to the NVIC, replacing the default routing
* to the PSP's GIC.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
aspeed_soc_ast27x0_coprocessor_get_irq(s, s->uart_dev));
/* FMC */
memory_region_init_alias(&a->fmc_alias, OBJECT(a), "fmc.alias",
&a->fmc->mmio, 0,
memory_region_size(&a->fmc->mmio));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_FMC],
&a->fmc_alias);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]),
"aspeed.ipc0",
sc->memmap[ASPEED_DEV_IPC0], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
"aspeed.ipc1",
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
"aspeed.pric0",
sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
"aspeed.pric1",
sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->otp),
"aspeed.otp",
sc->memmap[ASPEED_DEV_OTP], 0x800);
}
static const Property aspeed_27x0_coprocessor_properties[] = {
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
DEFINE_PROP_LINK("scuio", Aspeed27x0CoprocessorState, scuio,
TYPE_ASPEED_SCU, AspeedSCUState *),
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
AspeedSMCState *),
};
static void aspeed_soc_ast27x0_coprocessor_class_init(ObjectClass *klass,
const void *data)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
NULL
};
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_CLASS(klass);
/* Reason: The Aspeed Coprocessor can only be instantiated from a board */
dc->user_creatable = false;
dc->realize = aspeed_soc_ast27x0_coprocessor_realize;
device_class_set_props(dc, aspeed_27x0_coprocessor_properties);
sc->valid_cpu_types = valid_cpu_types;
sc->irqmap = aspeed_soc_ast27x0_coprocessor_irqmap;
sc->memmap = aspeed_soc_ast27x0_coprocessor_memmap;
}
static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
const void *data)
{
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_CLASS(klass);
c->intc_type = TYPE_ASPEED_2700SSP_INTC;
c->intcio_type = TYPE_ASPEED_2700SSP_INTCIO;
c->dram_remap_alias = ast27x0ssp_dram_remap_alias;
}
static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
const void *data)
{
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_CLASS(klass);
c->intc_type = TYPE_ASPEED_2700TSP_INTC;
c->intcio_type = TYPE_ASPEED_2700TSP_INTCIO;
c->dram_remap_alias = ast27x0tsp_dram_remap_alias;
}
static const TypeInfo aspeed_soc_ast27x0_coprocessor_types[] = {
{
.name = TYPE_ASPEED27X0_COPROCESSOR,
.parent = TYPE_ASPEED_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.class_size = sizeof(Aspeed27x0CoprocessorClass),
.instance_init = aspeed_soc_ast27x0_coprocessor_init,
.class_init = aspeed_soc_ast27x0_coprocessor_class_init,
.abstract = true,
},
{
.name = TYPE_ASPEED27X0SSP_COPROCESSOR,
.parent = TYPE_ASPEED27X0_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.class_init = aspeed_soc_ast27x0ssp_class_init,
},
{
.name = TYPE_ASPEED27X0TSP_COPROCESSOR,
.parent = TYPE_ASPEED27X0_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.class_init = aspeed_soc_ast27x0tsp_class_init,
},
};
DEFINE_TYPES(aspeed_soc_ast27x0_coprocessor_types)
aspeed_coprocessor.h
/*
* ASPEED Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ASPEED_COPROCESSOR_H
#define ASPEED_COPROCESSOR_H
#include "qom/object.h"
#include "hw/arm/aspeed_soc.h"
struct AspeedCoprocessorState {
DeviceState parent;
MemoryRegion *memory;
MemoryRegion sdram;
MemoryRegion *sram;
MemoryRegion sram_alias;
MemoryRegion uart_alias;
Clock *sysclk;
AspeedTimerCtrlState timerctrl;
SerialMM *uart;
int uart_dev;
};
#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
ASPEED_COPROCESSOR)
struct AspeedCoprocessorClass {
DeviceClass parent_class;
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
const hwaddr *memmap;
const int *irqmap;
};
struct Aspeed27x0CoprocessorState {
AspeedCoprocessorState parent;
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState pric[2];
UnimplementedDeviceState otp;
ARMv7MState armv7m;
MemoryRegion scu_alias;
MemoryRegion scuio_alias;
MemoryRegion fmc_alias;
Aspeed2700SCUState *scu;
AspeedSCUState *scuio;
AspeedSMCState *fmc;
};
/*
* TYPE_ASPEED27X0_COPROCESSOR is an abstract type shared by the SSP and TSP
* coprocessors: they use the exact same instance_init/realize logic and
* only differ in a handful of per-model constants (INTC subtype, and which
* SCU dram_remap_alias entries they map). Those constants live in
* Aspeed27x0CoprocessorClass and are set once by each concrete model's
* class_init (see aspeed_ast27x0-coprocessor.c). This is a reference/
* experimental merge of the former aspeed_ast27x0-ssp.c/-tsp.c, kept for
* comparison purposes.
*/
#define TYPE_ASPEED27X0_COPROCESSOR "aspeed27x0-coprocessor"
OBJECT_DECLARE_TYPE(Aspeed27x0CoprocessorState, Aspeed27x0CoprocessorClass,
ASPEED27X0_COPROCESSOR)
struct Aspeed27x0CoprocessorClass {
AspeedCoprocessorClass parent_class;
const char *intc_type;
const char *intcio_type;
/*
* Returns this coprocessor's own SCU dram-remap-alias array (already in
* the order it should be concatenated at this coprocessor's own SDRAM
* offset 0), and stores its length in *n.
*/
MemoryRegion *(*dram_remap_alias)(Aspeed2700SCUState *scu, int *n);
};
#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor"
#endif /* ASPEED_COPROCESSOR_H */
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 5c3f563dd5..8b747917d7 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c --- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -980,7 +980,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
case AST2700_SCU_SSP_CTRL_1:
case AST2700_SCU_SSP_CTRL_2:
mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
- &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ &a->ssp_dram_remap_alias[1] : &a->ssp_dram_remap_alias[0];
if (a->ssp_cpuid < 0 || mr == NULL) {
return;
}
@@ -993,7 +993,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
case AST2700_SCU_SSP_REMAP_ADDR_1:
case AST2700_SCU_SSP_REMAP_ADDR_2:
mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
- &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ &a->ssp_dram_remap_alias[1] : &a->ssp_dram_remap_alias[0];
if (a->ssp_cpuid < 0 || mr == NULL) {
return;
}
@@ -1005,7 +1005,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
case AST2700_SCU_SSP_REMAP_SIZE_1:
case AST2700_SCU_SSP_REMAP_SIZE_2:
mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
- &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ &a->ssp_dram_remap_alias[1] : &a->ssp_dram_remap_alias[0];
if (a->ssp_cpuid < 0 || mr == NULL) {
return;
}
@@ -1015,7 +1015,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
memory_region_transaction_commit();
break;
case AST2700_SCU_TSP_CTRL_1:
- mr = &a->dram_remap_alias[2];
+ mr = &a->tsp_dram_remap_alias[0];
if (a->tsp_cpuid < 0 || mr == NULL) {
return;
}
@@ -1026,7 +1026,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
memory_region_transaction_commit();
break;
case AST2700_SCU_TSP_REMAP_SIZE_2:
- mr = &a->dram_remap_alias[2];
+ mr = &a->tsp_dram_remap_alias[0];
if (a->tsp_cpuid < 0 || mr == NULL) {
return;
}
© 2016 - 2026 Red Hat, Inc.