[PATCH] hw/avr: Add limited support for avr gpio registers
[PATCH v5] hw/avr: Add limited support for avr gpio registers
1
Add some of these features for avr gpio:
1
Add some of these features for AVR GPIO:
2
2
3
  - GPIO I/O : PORTx registers
3
- GPIO I/O : PORTx registers
4
  - Data Direction : DDRx registers
4
- Data Direction : DDRx registers
5
- DDRx toggling : PINx registers
5
6
6
Following things are not supported yet:
7
Following things are not supported yet:
7
  - PINx registers
8
- MCUR registers
8
  - MCUR registers
9
  - Even though read/write for DDRx registers are
10
    implemented, actual direction controls are not
11
    supported yet.
12
9
13
Signed-off-by: Heecheol Yang <heecheol.yang@outlook.com>
10
Signed-off-by: Heecheol Yang <heecheol.yang@outlook.com>
14
---
11
---
15
 hw/avr/Kconfig             |   1 +
12
hw/avr/Kconfig | 1 +
16
 hw/avr/atmega.c            |   7 ++-
13
hw/avr/atmega.c | 7 +-
17
 hw/avr/atmega.h            |   2 +
14
hw/avr/atmega.h | 2 +
18
 hw/gpio/Kconfig            |   3 +
15
hw/gpio/Kconfig | 3 +
19
 hw/gpio/avr_gpio.c         | 117 +++++++++++++++++++++++++++++++++++++
16
hw/gpio/avr_gpio.c | 136 +++++++++++++++++++++++++++++++++++++
20
 hw/gpio/meson.build        |   2 +
17
hw/gpio/meson.build | 2 +
21
 include/hw/gpio/avr_gpio.h |  48 +++++++++++++++
18
include/hw/gpio/avr_gpio.h | 53 +++++++++++++++
22
 7 files changed, 178 insertions(+), 2 deletions(-)
19
7 files changed, 202 insertions(+), 2 deletions(-)
23
 create mode 100644 hw/gpio/avr_gpio.c
20
create mode 100644 hw/gpio/avr_gpio.c
24
 create mode 100644 include/hw/gpio/avr_gpio.h
21
create mode 100644 include/hw/gpio/avr_gpio.h
25
22
26
diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
23
diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
27
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/avr/Kconfig
25
--- a/hw/avr/Kconfig
29
+++ b/hw/avr/Kconfig
26
+++ b/hw/avr/Kconfig
30
@@ -XXX,XX +XXX,XX @@ config AVR_ATMEGA_MCU
27
@@ -XXX,XX +XXX,XX @@ config AVR_ATMEGA_MCU
31
     select AVR_TIMER16
28
select AVR_TIMER16
32
     select AVR_USART
29
select AVR_USART
33
     select AVR_POWER
30
select AVR_POWER
34
+    select AVR_GPIO
31
+ select AVR_GPIO
35
32
36
 config ARDUINO
33
config ARDUINO
37
     select AVR_ATMEGA_MCU
34
select AVR_ATMEGA_MCU
38
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
35
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
39
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/avr/atmega.c
37
--- a/hw/avr/atmega.c
41
+++ b/hw/avr/atmega.c
38
+++ b/hw/avr/atmega.c
42
@@ -XXX,XX +XXX,XX @@ static void atmega_realize(DeviceState *dev, Error
39
@@ -XXX,XX +XXX,XX @@ static void atmega_realize(DeviceState *dev, Error **errp)
43
**errp)
40
continue;
44
             continue;
41
}
45
         }
42
devname = g_strdup_printf("atmega-gpio-%c", 'a' + (char)i);
46
         devname = g_strdup_printf("atmega-gpio-%c", 'a' + (char)i);
43
- create_unimplemented_device(devname,
47
-        create_unimplemented_device(devname,
44
- OFFSET_DATA + mc->dev[idx].addr, 3);
48
-                                    OFFSET_DATA + mc->dev[idx].addr, 3);
45
+ object_initialize_child(OBJECT(dev), devname, &s->gpio[i],
49
+        object_initialize_child(OBJECT(dev), devname, &s->gpio[i],
46
+ TYPE_AVR_GPIO);
50
+                                TYPE_AVR_GPIO);
47
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
51
+        sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
48
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
52
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
49
+ OFFSET_DATA + mc->dev[idx].addr);
53
+            OFFSET_DATA + mc->dev[idx].addr);
50
g_free(devname);
54
         g_free(devname);
51
}
55
     }
52
56
57
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
53
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
58
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/avr/atmega.h
55
--- a/hw/avr/atmega.h
60
+++ b/hw/avr/atmega.h
56
+++ b/hw/avr/atmega.h
61
@@ -XXX,XX +XXX,XX @@
57
@@ -XXX,XX +XXX,XX @@
62
58
63
 #include "hw/char/avr_usart.h"
59
#include "hw/char/avr_usart.h"
64
 #include "hw/timer/avr_timer16.h"
60
#include "hw/timer/avr_timer16.h"
65
+#include "hw/gpio/avr_gpio.h"
61
+#include "hw/gpio/avr_gpio.h"
66
 #include "hw/misc/avr_power.h"
62
#include "hw/misc/avr_power.h"
67
 #include "target/avr/cpu.h"
63
#include "target/avr/cpu.h"
68
 #include "qom/object.h"
64
#include "qom/object.h"
69
@@ -XXX,XX +XXX,XX @@ struct AtmegaMcuState {
65
@@ -XXX,XX +XXX,XX @@ struct AtmegaMcuState {
70
     DeviceState *io;
66
DeviceState *io;
71
     AVRMaskState pwr[POWER_MAX];
67
AVRMaskState pwr[POWER_MAX];
72
     AVRUsartState usart[USART_MAX];
68
AVRUsartState usart[USART_MAX];
73
+    AVRGPIOState gpio[GPIO_MAX];
69
+ AVRGPIOState gpio[GPIO_MAX];
74
     AVRTimer16State timer[TIMER_MAX];
70
AVRTimer16State timer[TIMER_MAX];
75
     uint64_t xtal_freq_hz;
71
uint64_t xtal_freq_hz;
76
 };
72
};
77
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
73
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
78
index XXXXXXX..XXXXXXX 100644
74
index XXXXXXX..XXXXXXX 100644
79
--- a/hw/gpio/Kconfig
75
--- a/hw/gpio/Kconfig
80
+++ b/hw/gpio/Kconfig
76
+++ b/hw/gpio/Kconfig
81
@@ -XXX,XX +XXX,XX @@ config GPIO_KEY
77
@@ -XXX,XX +XXX,XX @@ config GPIO_KEY
82
78
83
 config SIFIVE_GPIO
79
config SIFIVE_GPIO
84
     bool
80
bool
85
+
81
+
86
+config AVR_GPIO
82
+config AVR_GPIO
87
+    bool
83
+ bool
88
diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
84
diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
89
new file mode 100644
85
new file mode 100644
90
index XXXXXXX..XXXXXXX
86
index XXXXXXX..XXXXXXX
91
--- /dev/null
87
--- /dev/null
92
+++ b/hw/gpio/avr_gpio.c
88
+++ b/hw/gpio/avr_gpio.c
...
...
101
+ * published by the Free Software Foundation; either version 2 or
97
+ * published by the Free Software Foundation; either version 2 or
102
+ * (at your option) version 3 of the License.
98
+ * (at your option) version 3 of the License.
103
+ *
99
+ *
104
+ * This program is distributed in the hope that it will be useful,
100
+ * This program is distributed in the hope that it will be useful,
105
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
101
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
106
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
102
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
107
+ * GNU General Public License for more details.
103
+ * GNU General Public License for more details.
108
+ *
104
+ *
109
+ * You should have received a copy of the GNU General Public License along
105
+ * You should have received a copy of the GNU General Public License along
110
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
106
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
111
+ */
107
+ */
112
+#include "qemu/osdep.h"
108
+#include "qemu/osdep.h"
113
+#include "qemu/log.h"
109
+#include "qemu/log.h"
114
+#include "qemu/module.h"
110
+#include "qemu/module.h"
115
+#include "qemu/timer.h"
111
+#include "qemu/osdep.h"
116
+#include "qapi/error.h"
112
+#include "qapi/error.h"
117
+#include "hw/sysbus.h"
113
+#include "hw/sysbus.h"
118
+#include "hw/irq.h"
114
+#include "hw/irq.h"
119
+#include "hw/gpio/avr_gpio.h"
115
+#include "hw/gpio/avr_gpio.h"
120
+#include "hw/qdev-properties.h"
116
+#include "hw/qdev-properties.h"
121
+#include "chardev/char-fe.h"
122
+
117
+
123
+static void avr_gpio_reset(DeviceState *dev)
118
+static void avr_gpio_reset(DeviceState *dev)
124
+{
119
+{
125
+    AVRGPIOState *gpio = AVR_GPIO(dev);
120
+ AVRGPIOState *gpio = AVR_GPIO(dev);
126
+    gpio->ddr_val = 0u;
121
+ gpio->reg.pin = 0u;
127
+    gpio->port_val = 0u;
122
+ gpio->reg.ddr = 0u;
128
+}
123
+ gpio->reg.port = 0u;
129
+static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int
124
+}
130
size)
125
+
131
+{
126
+static void avr_gpio_write_port(AVRGPIOState *s, uint64_t value)
132
+    AVRGPIOState *s = (AVRGPIOState *)opaque;
127
+{
133
+    switch (offset) {
128
+ uint8_t pin;
134
+    case GPIO_PIN:
129
+ uint8_t cur_port_val = s->reg.port;
135
+        /* Not implemented yet */
130
+ uint8_t cur_ddr_val = s->reg.ddr;
136
+        break;
131
+
137
+    case GPIO_DDR:
132
+ for (pin = 0u; pin < 8u ; pin++) {
138
+        return s->ddr_val;
133
+ uint8_t cur_port_pin_val = cur_port_val & 0x01u;
139
+        break;
134
+ uint8_t cur_ddr_pin_val = cur_ddr_val & 0x01u;
140
+    case GPIO_PORT:
135
+ uint8_t new_port_pin_val = value & 0x01u;
141
+        return s->port_val;
136
+
142
+    default:
137
+ if (cur_ddr_pin_val && (cur_port_pin_val != new_port_pin_val)) {
143
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %lx\n",
138
+ qemu_set_irq(s->out[pin], new_port_pin_val);
144
+                __func__, offset);
139
+ }
145
+        break;
140
+ cur_port_val >>= 1u;
146
+    }
141
+ cur_ddr_val >>= 1u;
147
+    return 0;
142
+ value >>= 1u;
143
+ }
144
+ s->reg.port = value & s->reg.ddr;
145
+}
146
+static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int size)
147
+{
148
+ AVRGPIOState *s = (AVRGPIOState *)opaque;
149
+ switch (offset) {
150
+ case GPIO_PIN:
151
+ return s->reg.pin;
152
+ case GPIO_DDR:
153
+ return s->reg.ddr;
154
+ case GPIO_PORT:
155
+ return s->reg.port;
156
+ default:
157
+ g_assert_not_reached();
158
+ break;
159
+ }
160
+ return 0;
148
+}
161
+}
149
+
162
+
150
+static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value,
163
+static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value,
151
+                                unsigned int size)
164
+ unsigned int size)
152
+{
165
+{
153
+    AVRGPIOState *s = (AVRGPIOState *)opaque;
166
+ AVRGPIOState *s = (AVRGPIOState *)opaque;
154
+    switch (offset) {
167
+ value = value & 0xF;
155
+    case GPIO_PIN:
168
+ switch (offset) {
156
+        /* Not implemented yet */
169
+ case GPIO_PIN:
157
+        break;
170
+ s->reg.pin = value;
158
+    case GPIO_DDR:
171
+ s->reg.port ^= s->reg.pin;
159
+        s->ddr_val = value & 0xF;
172
+ break;
160
+        break;
173
+ case GPIO_DDR:
161
+    case GPIO_PORT:
174
+ s->reg.ddr = value;
162
+        s->port_val = value & 0xF;
175
+ break;
163
+        break;
176
+ case GPIO_PORT:
164
+    default:
177
+ avr_gpio_write_port(s, value);
165
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %lx\n",
178
+ break;
166
+                __func__, offset);
179
+ default:
167
+        break;
180
+ g_assert_not_reached();
168
+    }
181
+ break;
182
+ }
169
+}
183
+}
170
+
184
+
171
+static const MemoryRegionOps avr_gpio_ops = {
185
+static const MemoryRegionOps avr_gpio_ops = {
172
+    .read = avr_gpio_read,
186
+ .read = avr_gpio_read,
173
+    .write = avr_gpio_write,
187
+ .write = avr_gpio_write,
174
+    .endianness = DEVICE_NATIVE_ENDIAN,
188
+ .endianness = DEVICE_NATIVE_ENDIAN,
175
+};
189
+};
176
+
190
+
177
+static void avr_gpio_init(Object *obj)
191
+static void avr_gpio_init(Object *obj)
178
+{
192
+{
179
+    AVRGPIOState *s = AVR_GPIO(obj);
193
+ AVRGPIOState *s = AVR_GPIO(obj);
180
+    memory_region_init_io(&s->mmio, obj, &avr_gpio_ops, s,
194
+ qdev_init_gpio_out(DEVICE(obj), s->out, ARRAY_SIZE(s->out));
181
TYPE_AVR_GPIO, 3);
195
+ memory_region_init_io(&s->mmio, obj, &avr_gpio_ops, s, TYPE_AVR_GPIO, 3);
182
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
196
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
183
+    s->enabled = true;
184
+}
197
+}
185
+static void avr_gpio_realize(DeviceState *dev, Error **errp)
198
+static void avr_gpio_realize(DeviceState *dev, Error **errp)
186
+{
199
+{
187
+    avr_gpio_reset(dev);
200
+ /* Do nothing currently */
188
+}
201
+}
189
+
202
+
190
+
203
+
191
+static void avr_gpio_class_init(ObjectClass *klass, void *data)
204
+static void avr_gpio_class_init(ObjectClass *klass, void *data)
192
+{
205
+{
193
+    DeviceClass *dc = DEVICE_CLASS(klass);
206
+ DeviceClass *dc = DEVICE_CLASS(klass);
194
+
207
+
195
+    dc->reset = avr_gpio_reset;
208
+ dc->reset = avr_gpio_reset;
196
+    dc->realize = avr_gpio_realize;
209
+ dc->realize = avr_gpio_realize;
197
+}
210
+}
198
+
211
+
199
+static const TypeInfo avr_gpio_info = {
212
+static const TypeInfo avr_gpio_info = {
200
+    .name          = TYPE_AVR_GPIO,
213
+ .name = TYPE_AVR_GPIO,
201
+    .parent        = TYPE_SYS_BUS_DEVICE,
214
+ .parent = TYPE_SYS_BUS_DEVICE,
202
+    .instance_size = sizeof(AVRGPIOState),
215
+ .instance_size = sizeof(AVRGPIOState),
203
+    .instance_init = avr_gpio_init,
216
+ .instance_init = avr_gpio_init,
204
+    .class_init    = avr_gpio_class_init,
217
+ .class_init = avr_gpio_class_init,
205
+};
218
+};
206
+
219
+
207
+static void avr_gpio_register_types(void)
220
+static void avr_gpio_register_types(void)
208
+{
221
+{
209
+    type_register_static(&avr_gpio_info);
222
+ type_register_static(&avr_gpio_info);
210
+}
223
+}
211
+
224
+
212
+type_init(avr_gpio_register_types)
225
+type_init(avr_gpio_register_types)
213
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
226
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
214
index XXXXXXX..XXXXXXX 100644
227
index XXXXXXX..XXXXXXX 100644
215
--- a/hw/gpio/meson.build
228
--- a/hw/gpio/meson.build
216
+++ b/hw/gpio/meson.build
229
+++ b/hw/gpio/meson.build
217
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true:
230
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
218
files('omap_gpio.c'))
231
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
219
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
232
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
220
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
233
softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
221
 softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true:
222
files('sifive_gpio.c'))
223
+
234
+
224
+softmmu_ss.add(when: 'CONFIG_AVR_GPIO', if_true: files('avr_gpio.c'))
235
+softmmu_ss.add(when: 'CONFIG_AVR_GPIO', if_true: files('avr_gpio.c'))
225
diff --git a/include/hw/gpio/avr_gpio.h b/include/hw/gpio/avr_gpio.h
236
diff --git a/include/hw/gpio/avr_gpio.h b/include/hw/gpio/avr_gpio.h
226
new file mode 100644
237
new file mode 100644
227
index XXXXXXX..XXXXXXX
238
index XXXXXXX..XXXXXXX
...
...
238
+ * published by the Free Software Foundation; either version 2 or
249
+ * published by the Free Software Foundation; either version 2 or
239
+ * (at your option) version 3 of the License.
250
+ * (at your option) version 3 of the License.
240
+ *
251
+ *
241
+ * This program is distributed in the hope that it will be useful,
252
+ * This program is distributed in the hope that it will be useful,
242
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
253
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
243
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
254
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
244
+ * GNU General Public License for more details.
255
+ * GNU General Public License for more details.
245
+ *
256
+ *
246
+ * You should have received a copy of the GNU General Public License along
257
+ * You should have received a copy of the GNU General Public License along
247
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
258
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
248
+ */
259
+ */
249
+
260
+
250
+#ifndef AVR_GPIO_H
261
+#ifndef AVR_GPIO_H
251
+#define AVR_GPIO_H
262
+#define AVR_GPIO_H
252
+
263
+
253
+#include "hw/sysbus.h"
264
+#include "hw/sysbus.h"
254
+#include "qom/object.h"
265
+#include "qom/object.h"
255
+#include "chardev/char-fe.h"
256
+
266
+
257
+/* Offsets of registers. */
267
+/* Offsets of registers. */
258
+#define GPIO_PIN   0x00
268
+#define GPIO_PIN 0x00
259
+#define GPIO_DDR   0x01
269
+#define GPIO_DDR 0x01
260
+#define GPIO_PORT  0x02
270
+#define GPIO_PORT 0x02
261
+
271
+
262
+#define TYPE_AVR_GPIO "avr-gpio"
272
+#define TYPE_AVR_GPIO "avr-gpio"
263
+OBJECT_DECLARE_SIMPLE_TYPE(AVRGPIOState, AVR_GPIO)
273
+OBJECT_DECLARE_SIMPLE_TYPE(AVRGPIOState, AVR_GPIO)
274
+#define AVR_GPIO_COUNT 8
264
+
275
+
265
+struct AVRGPIOState {
276
+struct AVRGPIOState {
266
+    /*< private >*/
277
+ /*< private >*/
267
+    SysBusDevice parent_obj;
278
+ SysBusDevice parent_obj;
268
+
279
+
269
+    /*< public >*/
280
+ /*< public >*/
270
+    MemoryRegion mmio;
281
+ MemoryRegion mmio;
271
+
282
+
272
+    uint8_t ddr_val;
283
+ struct {
273
+    uint8_t port_val;
284
+ uint8_t pin;
274
+    bool enabled;
285
+ uint8_t ddr;
286
+ uint8_t port;
287
+ } reg;
288
+
289
+ /* PORTx data changed IRQs */
290
+ qemu_irq out[8u];
275
+
291
+
276
+};
292
+};
277
+
293
+
278
+#endif /* AVR_GPIO_H */
294
+#endif /* AVR_GPIO_H */
279
--
295
--
280
2.17.1
296
2.17.1
297
298
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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