Ping. Just checking if anyone got a chance to review this patch series. NXP Confidential > -----Original Message----- > From: Gaurav Sharma <gaurav.sharma_7@nxp.com> > Sent: 07 October 2026 15:41 > To: qemu-devel@nongnu.org > Cc: qemu-arm@nongnu.org; pbonzini@redhat.com; > peter.maydell@linaro.org; shentey@gmail.com; > pierrick.bouvier@oss.qualcomm.com; Gaurav Sharma > <gaurav.sharma_7@nxp.com> > Subject: [PATCHv4 00/11] hw/arm: Adding Cortex-M7 Asymmetric > Multiprocessing boot support for i.MX8MP > > Changes in v1: > > This series adds Asymmetric Multiprocessing (AMP) boot support for the > Cortex-M7 core on the i.MX8MP SoC. The M7 firmware can be loaded and > started from Linux running on the Cortex-A53 cores via the remoteproc > framework. > > The series introduces the following peripheral models needed for AMP: > - GPC (General Power Controller) > - GPR (General Purpose Registers) > - SRC (System Reset Controller) authored by Bernhard Beschow > <shentey@gmail.com> > - MU (Messaging Unit) > - Extends the CCM with M7 clock outputs and wires into the i.MX8MP SoC > - Enable Cortex-M7 boot in i.MX8MP EVK functional test > > Changes in v2: > > - Removed the usage of device_class_set_legacy_reset in imx8mp gpc,gpr,mu > and > src. > - Removed the usage of 'smp' , 'maxcpus' and 'enable-cm7' to make the > invocation simpler. > - Cleaned up imx8mp_src by removing redundant/unused code. > - Updated Maintainers and improved the imx8mp documentation > > Changes in v3: > > - Added a new patch for smp removal from test_imx8mp_evk.py. > - Added a new patch to introduce IRQ splitting for i.MX8MP AMP interrupt > routing. > - Added a new patch to rename FSL_IMX8MP_NUM_CPUS to > FSL_IMX8MP_NUM_A53, > since M7 is being introduced now. > - In GPR, parent_phases moved from global variable to class struct > - M7 reset handling moved from the machine to SRC device model. > - Added ITCM and DTCM memory regions to support zephyr firmware > loading. > > Changes in v4: > > - Move independent MAINTAINERS, CPU renaming and functional-test > cleanups to the beginning of the series > - Created a separate patch for ITCM and DTCM modeling. > - Move IRQ splitter infrastructure before Cortex-M7 integration > > Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> > > Gaurav Sharma (11): > MAINTAINERS: Merge MCIMX8MM-EVK and MCIMX8MP-EVK entries > hw/arm: Rename FSL_IMX8MP_NUM_CPUS to FSL_IMX8MP_NUM_A53 > tests/functional: Fix i.MX8MP EVK SMP configuration > hw/misc: Add i.MX8MP GPC (General Power Controller) IP > hw/misc: Add GPR (General Purpose Register) IP to iMX8MP > hw/misc: Add SRC (System Reset Controller) to i.MX8MP > hw/misc: Add MU (Messaging Unit) IP to i.MX8MP device model > hw/misc: Extend i.MX8MP CCM with Cortex-M7 clock outputs > hw/arm: Add ITCM and DTCM memory regions to i.MX8MP > hw/arm: Add IRQ splitter for i.MX8MP AMP interrupt routing > hw/arm: Enable Cortex-M7 AMP boot on i.MX8MP > > MAINTAINERS | 13 +- > docs/system/arm/imx8m.rst | 186 +++++++++ > hw/arm/Kconfig | 4 + > hw/arm/fsl-imx8mp.c | 229 +++++++++-- > hw/arm/imx8mp-evk.c | 5 +- > hw/misc/Kconfig | 12 + > hw/misc/imx8mp_ccm.c | 9 + > hw/misc/imx8mp_gpc.c | 146 +++++++ > hw/misc/imx8mp_gpr.c | 155 ++++++++ > hw/misc/imx8mp_mu.c | 346 +++++++++++++++++ > hw/misc/imx8mp_src.c | 397 ++++++++++++++++++++ > hw/misc/meson.build | 4 + > hw/misc/trace-events | 5 + > include/hw/arm/fsl-imx8mp.h | 32 +- > include/hw/misc/imx8mp_ccm.h | 3 + > include/hw/misc/imx8mp_gpc.h | 34 ++ > include/hw/misc/imx8mp_gpr.h | 62 +++ > include/hw/misc/imx8mp_mu.h | 53 +++ > include/hw/misc/imx8mp_src.h | 47 +++ > tests/functional/aarch64/test_imx8mp_evk.py | 1 - > 20 files changed, 1696 insertions(+), 47 deletions(-) create mode 100644 > hw/misc/imx8mp_gpc.c create mode 100644 hw/misc/imx8mp_gpr.c create > mode 100644 hw/misc/imx8mp_mu.c create mode 100644 > hw/misc/imx8mp_src.c create mode 100644 include/hw/misc/imx8mp_gpc.h > create mode 100644 include/hw/misc/imx8mp_gpr.h create mode 100644 > include/hw/misc/imx8mp_mu.h create mode 100644 > include/hw/misc/imx8mp_src.h > > -- > 2.34.1
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