[v1] target/riscv: Make hpmcounterh return the upper 32-bits

[PATCH v1] target/riscv: Make hpmcounterh return the upper 32-bits

Posted by Portia Stephens 1 week, 4 days ago

The counter value was not being bitshifted for a hpmcounterh read
resulting in hpmcounterh returning the bottom 32-bits.

Signed-off-by: Portia Stephens <portias@tenstorrent.com>
---
  target/riscv/csr.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cfd076b368..c522533807 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1389,8 +1389,9 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState 
*env, target_ulong *val,
       */
      if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
          riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
-        *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
-                                                    ctr_prev + ctr_val;
+        uint64_t cntr = riscv_pmu_ctr_get_fixed_counters_val(env, 
ctr_idx) -
+  ctr_prev + ctr_val;
+        *val = extract64(cntr, start, length);
      } else {
          *val = ctr_val;
      }
--
2.43.0

Re: [PATCH v1] target/riscv: Make hpmcounterh return the upper 32-bits

Posted by Alistair Francis 1 week, 4 days ago

On Tue, May 19, 2026 at 2:04 PM Portia Stephens
<portias@oss.tenstorrent.com> wrote:
>
> The counter value was not being bitshifted for a hpmcounterh read
> resulting in hpmcounterh returning the bottom 32-bits.
>

Fixes:  cfc96df65e01 ("target/riscv: Remove upper_half from
riscv_pmu_ctr_get_fixed_counters_val")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3498
Cc: qemu-stable@nongnu.org

> Signed-off-by: Portia Stephens <portias@tenstorrent.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

> ---
>   target/riscv/csr.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index cfd076b368..c522533807 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1389,8 +1389,9 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState
> *env, target_ulong *val,
>        */
>       if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
>           riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
> -        *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
> -                                                    ctr_prev + ctr_val;
> +        uint64_t cntr = riscv_pmu_ctr_get_fixed_counters_val(env,
> ctr_idx) -
> +  ctr_prev + ctr_val;
> +        *val = extract64(cntr, start, length);

Some patch issues here

Alistair

>       } else {
>           *val = ctr_val;
>       }
> --
> 2.43.0
>
>