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> -----Original Message-----
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> -----Original Message-----
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> From: Nicolin Chen <nicolinc@nvidia.com>
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> From: Nathan Chen <nathanc@nvidia.com>
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> Sent: Thursday, January 23, 2025 4:10 AM
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> Sent: Friday, November 22, 2024 1:42 AM
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> To: Donald Dutile <ddutile@redhat.com>
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> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
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> Cc: Shameerali Kolothum Thodi
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> Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org;
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> <shameerali.kolothum.thodi@huawei.com>; eric.auger@redhat.com; Peter
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> eric.auger@redhat.com; peter.maydell@linaro.org; jgg@nvidia.com;
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> Maydell <peter.maydell@linaro.org>; Jason Gunthorpe <jgg@nvidia.com>;
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> ddutile@redhat.com; Linuxarm <linuxarm@huawei.com>; Wangzhou (B)
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> Daniel P. Berrangé <berrange@redhat.com>; qemu-arm@nongnu.org;
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> <wangzhou1@hisilicon.com>; jiangkunkun <jiangkunkun@huawei.com>;
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> qemu-devel@nongnu.org; Linuxarm <linuxarm@huawei.com>; Wangzhou
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> (B) <wangzhou1@hisilicon.com>; jiangkunkun <jiangkunkun@huawei.com>;
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> Jonathan Cameron <jonathan.cameron@huawei.com>;
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> Jonathan Cameron <jonathan.cameron@huawei.com>;
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> zhangfei.gao@linaro.org
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> zhangfei.gao@linaro.org; Nicolin Chen <nicolinc@nvidia.com>
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> Subject: Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable
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> Subject: Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable
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> nested SMMUv3
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> nested SMMUv3
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>
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>
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> Hi Don,
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> >> Also as a heads up, I've added support for auto-inserting PCIe switch
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> >> between the PXB and GPUs in libvirt to attach multiple devices to a
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> SMMU
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> >> node per libvirt's documentation - "If you intend to plug multiple
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> >> devices into a pcie-expander-bus, you must connect a
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> >> pcie-switch-upstream-port to the pcie-root-port that is plugged into the
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> >> pcie-expander-bus, and multiple pcie-switch-downstream-ports to the
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> >> pcie-switch-upstream-port". Future unit-tests should follow this
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> >> topology configuration.
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> >
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> > Ok. Could you please give me an example Qemu equivalent command
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> option,
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> > if possible, for the above case. I am not that familiar with libvirt
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> and I would
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> > also like to test the above scenario.
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>
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>
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> On Fri, Jan 10, 2025 at 11:05:24PM -0500, Donald Dutile wrote:
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> You can use "-device x3130-upstream" for the upstream switch port, and
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> > On 1/8/25 11:45 PM, Nicolin Chen wrote:
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> "-device xio3130-downstream" for the downstream port:
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> > > On Mon, Dec 16, 2024 at 10:01:29AM +0000, Shameerali Kolothum Thodi
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> wrote:
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> > > > And patches prior to this commit adds that support:
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> > > > 4ccdbe3: ("cover-letter: Add HW accelerated nesting support for arm
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> > > > SMMUv3")
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> > > >
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> > > > Nicolin is soon going to send out those for review. Or I can include
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> > > > those in this series so that it gives a complete picture. Nicolin?
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> > >
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> > > Just found that I forgot to reply this one...sorry
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> > >
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> > > I asked Don/Eric to take over that vSMMU series:
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> > > https://lore.kernel.org/qemu-devel/Zy0jiPItu8A3wNTL@Asurada-Nvidia/
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> > > (The majority of my effort has been still on the kernel side:
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> > > previously vIOMMU/vDEVICE, and now vEVENTQ/MSI/vCMDQ..)
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> > >
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> > > Don/Eric, is there any update from your side?
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> > >
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> > Apologies for delayed response, been at customer site, and haven't been
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> keeping up w/biz email.
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> > Eric is probably waiting for me to get back and chat as well.
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> > Will look to reply early next week.
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>
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>
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> I wonder if we can make some progress in Feb? If so, we can start
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> -device pxb-pcie,bus_nr=250,id=pci.1,bus=pcie.0,addr=0x1 \
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> to wrap up the iommufd uAPI patches for HWPT, which was a part of
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> -device pcie-root-port,id=pci.2,bus=pci.1,addr=0x0 \
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> intel's series but never got sent since their emulated series is
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> -device x3130-upstream,id=pci.3,bus=pci.2,addr=0x0 \
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> seemingly still pending?
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> -device xio3130-
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> downstream,id=pci.4,bus=pci.3,addr=0x0,chassis=17,port=1 \
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> -device vfio-pci,host=0009:01:00.0,id=hostdev0,bus=pci.4,addr=0x0 \
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> -device arm-smmuv3-nested,pci-bus=pci.1
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I think these are the 5 patches that we require from Intel pass-through series,
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Thanks. Just wondering why libvirt mandates usage of pcie-switch for multiple
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device plugging rather than just using pcie-root-ports?
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vfio/iommufd: Implement [at|de]tach_hwpt handlers
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Please let me if there is any advantage in doing so that you are aware of.
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vfio/iommufd: Implement HostIOMMUDeviceClass::realize_late() handler
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HostIOMMUDevice: Introduce realize_late callback
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vfio/iommufd: Add properties and handlers to TYPE_HOST_IOMMU_DEVICE_IOMMUFD
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backends/iommufd: Add helpers for invalidating user-managed HWPT
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See the commits from here,
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https://github.com/hisilicon/qemu/commit/bbdc65af38fa5723f1bd9b026e292730901f57b5
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[CC Zhenzhong]
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Hi Zhenzhong,
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Just wondering what your plans are for the above patches. If it make sense and you
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are fine with it, I think it is a good idea one of us can pick up those from that series
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and sent out separately so that it can get some review and take it forward.
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Thanks,
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Thanks,
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Shameer
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Shameer
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