[PULL 00/35] tcg patch queue
[PULL 0/4] tcg patch queue
1
Dangit, forgot the PULL tag.
1
Pretty small still, but there are two patches that ought
2
to get backported to stable, so no point in delaying.
2
3
3
r~
4
r~
4
5
5
On 11/6/23 18:48, Richard Henderson wrote:
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
6
> The following changes since commit 3e01f1147a16ca566694b97eafc941d62fa1e8d8:
7
7
>
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
8
> Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging (2023-11-06 09:34:22 +0800)
9
9
>
10
are available in the Git repository at:
10
> are available in the Git repository at:
11
11
>
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
12
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231106
13
13
>
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
14
> for you to fetch changes up to d36ce28be424385fc9f7273bf5c15ce815b5cf4e:
15
15
>
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
16
> tcg/sparc64: Implement tcg_out_extrl_i64_i32 (2023-11-06 10:48:46 -0800)
17
17
>
18
----------------------------------------------------------------
18
> ----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
19
> util: Add cpuinfo for loongarch64
20
tcg/riscv: Fix StoreStore barrier generation
20
> tcg/loongarch64: Use cpuinfo.h
21
include/exec: Introduce fpst alias in helper-head.h.inc
21
> tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128
22
target/sparc: Use memcpy() and remove memcpy32()
22
> host/include/loongarch64: Add atomic16 load and store
23
23
> tcg: Move expanders out of line
24
----------------------------------------------------------------
24
> tcg/mips: Always implement movcond
25
Philippe Mathieu-Daudé (1):
25
> tcg/mips: Implement neg opcodes
26
target/sparc: Use memcpy() and remove memcpy32()
26
> tcg/loongarch64: Implement neg opcodes
27
27
> tcg: Make movcond and neg required opcodes
28
Richard Henderson (2):
28
> tcg: Optimize env memory operations
29
tcg: Reset free_temps before tcg_optimize
29
> tcg: Canonicalize sub of immediate to add
30
include/exec: Introduce fpst alias in helper-head.h.inc
30
> tcg/sparc64: Implement tcg_out_extrl_i64_i32
31
31
>
32
Roman Artemev (1):
32
> ----------------------------------------------------------------
33
tcg/riscv: Fix StoreStore barrier generation
33
> Richard Henderson (35):
34
34
> accel/tcg: Move HMP info jit and info opcount code
35
include/tcg/tcg-temp-internal.h | 6 ++++++
35
> tcg: Add C_N2_I1
36
accel/tcg/plugin-gen.c | 2 +-
36
> tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128
37
target/sparc/win_helper.c | 26 ++++++++------------------
37
> util: Add cpuinfo for loongarch64
38
tcg/tcg.c | 5 ++++-
38
> tcg/loongarch64: Use cpuinfo.h
39
include/exec/helper-head.h.inc | 3 +++
39
> host/include/loongarch64: Add atomic16 load and store
40
tcg/riscv/tcg-target.c.inc | 2 +-
40
> accel/tcg: Remove redundant case in store_atom_16
41
6 files changed, 23 insertions(+), 21 deletions(-)
41
> accel/tcg: Fix condition for store_atom_insert_al16
42
42
> tcg: Mark tcg_gen_op* as noinline
43
> tcg: Move tcg_gen_op* out of line
44
> tcg: Move generic expanders out of line
45
> tcg: Move 32-bit expanders out of line
46
> tcg: Move 64-bit expanders out of line
47
> tcg: Move vec_gen_* declarations to tcg-internal.h
48
> tcg: Move tcg_gen_opN declarations to tcg-internal.h
49
> tcg: Unexport tcg_gen_op*_{i32,i64}
50
> tcg: Move tcg_constant_* out of line
51
> tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line
52
> tcg: Move tcg_temp_free_* out of line
53
> tcg/mips: Split out tcg_out_setcond_int
54
> tcg/mips: Always implement movcond
55
> tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}
56
> tcg/mips: Implement neg opcodes
57
> tcg/loongarch64: Implement neg opcodes
58
> tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
59
> tcg: Don't free vector results
60
> tcg/optimize: Pipe OptContext into reset_ts
61
> tcg/optimize: Split out cmp_better_copy
62
> tcg/optimize: Optimize env memory operations
63
> tcg: Eliminate duplicate env store operations
64
> tcg/optimize: Split out arg_new_constant
65
> tcg: Canonicalize subi to addi during opcode generation
66
> tcg/optimize: Canonicalize subi to addi during optimization
67
> tcg/optimize: Canonicalize sub2 with constants to add2
68
> tcg/sparc64: Implement tcg_out_extrl_i64_i32
69
>
70
> accel/tcg/internal-common.h | 2 -
71
> host/include/loongarch64/host/atomic128-ldst.h | 52 ++
72
> host/include/loongarch64/host/cpuinfo.h | 21 +
73
> .../loongarch64/host/load-extract-al16-al8.h | 39 ++
74
> host/include/loongarch64/host/store-insert-al16.h | 12 +
75
> include/exec/cputlb.h | 1 -
76
> include/tcg/tcg-op-common.h | 538 ++---------------
77
> include/tcg/tcg-opc.h | 8 +-
78
> include/tcg/tcg-temp-internal.h | 56 +-
79
> include/tcg/tcg.h | 82 ---
80
> tcg/aarch64/tcg-target.h | 4 -
81
> tcg/arm/tcg-target.h | 2 -
82
> tcg/i386/tcg-target.h | 4 -
83
> tcg/loongarch64/tcg-target-con-set.h | 2 +-
84
> tcg/loongarch64/tcg-target.h | 12 +-
85
> tcg/mips/tcg-target.h | 4 -
86
> tcg/ppc/tcg-target.h | 4 -
87
> tcg/riscv/tcg-target.h | 4 -
88
> tcg/s390x/tcg-target.h | 4 -
89
> tcg/sparc64/tcg-target.h | 4 -
90
> tcg/tcg-internal.h | 18 +
91
> tcg/tci/tcg-target.h | 4 -
92
> accel/tcg/cputlb.c | 17 +-
93
> accel/tcg/monitor.c | 154 +++++
94
> accel/tcg/translate-all.c | 127 ----
95
> tcg/optimize.c | 370 ++++++++++--
96
> tcg/tcg-op-gvec.c | 112 ++--
97
> tcg/tcg-op.c | 636 ++++++++++++++++-----
98
> tcg/tcg.c | 131 ++++-
99
> tcg/tci.c | 2 -
100
> util/cpuinfo-loongarch.c | 35 ++
101
> accel/tcg/ldst_atomicity.c.inc | 14 +-
102
> tcg/loongarch64/tcg-target.c.inc | 34 +-
103
> tcg/mips/tcg-target.c.inc | 329 +++++------
104
> tcg/sparc64/tcg-target.c.inc | 5 +
105
> util/meson.build | 2 +
106
> 36 files changed, 1535 insertions(+), 1310 deletions(-)
107
> create mode 100644 host/include/loongarch64/host/atomic128-ldst.h
108
> create mode 100644 host/include/loongarch64/host/cpuinfo.h
109
> create mode 100644 host/include/loongarch64/host/load-extract-al16-al8.h
110
> create mode 100644 host/include/loongarch64/host/store-insert-al16.h
111
> create mode 100644 util/cpuinfo-loongarch.c
diff view generated by jsdifflib
New patch
[PULL 1/4] tcg: Reset free_temps before tcg_optimize
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
1
4
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
New patch
[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
1
From: Roman Artemev <roman.artemev@syntacore.com>
1
2
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
New patch
[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/helper-head.h.inc | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
13
+++ b/include/exec/helper-head.h.inc
14
@@ -XXX,XX +XXX,XX @@
15
#define dh_alias_ptr ptr
16
#define dh_alias_cptr ptr
17
#define dh_alias_env ptr
18
+#define dh_alias_fpst ptr
19
#define dh_alias_void void
20
#define dh_alias_noreturn noreturn
21
#define dh_alias(t) glue(dh_alias_, t)
22
@@ -XXX,XX +XXX,XX @@
23
#define dh_ctype_ptr void *
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
38
--
39
2.43.0
40
41
diff view generated by jsdifflib
New patch
[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Rather than manually copying each register, use
4
the libc memcpy(), which is well optimized nowadays.
5
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
14
1 file changed, 8 insertions(+), 18 deletions(-)
15
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
19
+++ b/target/sparc/win_helper.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "exec/helper-proto.h"
22
#include "trace.h"
23
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
25
-{
26
- dst[0] = src[0];
27
- dst[1] = src[1];
28
- dst[2] = src[2];
29
- dst[3] = src[3];
30
- dst[4] = src[4];
31
- dst[5] = src[5];
32
- dst[6] = src[6];
33
- dst[7] = src[7];
34
-}
35
-
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
37
{
38
/* put the modified wrap registers at their proper location */
39
if (env->cwp == env->nwindows - 1) {
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
42
+ sizeof(env->gregs));
43
}
44
env->cwp = new_cwp;
45
46
/* put the wrap registers at their temporary location */
47
if (new_cwp == env->nwindows - 1) {
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
50
+ sizeof(env->gregs));
51
}
52
env->regwptr = env->regbase + (new_cwp * 16);
53
}
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
55
dst = get_gl_gregset(env, env->gl);
56
57
if (src != dst) {
58
- memcpy32(dst, env->gregs);
59
- memcpy32(env->gregs, src);
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
62
}
63
}
64
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
66
/* Switch global register bank */
67
src = get_gregset(env, new_pstate_regs);
68
dst = get_gregset(env, pstate_regs);
69
- memcpy32(dst, env->gregs);
70
- memcpy32(env->gregs, src);
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
73
} else {
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
75
}
76
--
77
2.43.0
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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