This series removes the UART _DSD clock property and _CCA, adds
_STA = 0x0f, and updates the expected DSDT blobs.

It also changes the FDT clock-frequency from 100000000 to 1843200 Hz
to match the emulated UART model. The FDT clock property is retained.

Changes since v3:
- Add a separate patch to correct the FDT UART clock frequency.
- Carry Bibo Mao's Reviewed-by for the ACPI change.
- Clarify the ACPI commit message.

Testing:
- All five LoongArch ACPI bios-tables-test subtests pass.
- The generated DTB reports clock-frequency = 1843200 for all four
  UART nodes.

pillow (4):
  bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.*
  hw/loongarch/virt-acpi-build: Drop UART _DSD clock and add _STA
  tests/data/acpi/loongarch64: Update expected DSDT.*
  hw/loongarch/virt: Fix UART clock frequency in FDT

 hw/loongarch/virt-acpi-build.c                |  12 +-----------
 hw/loongarch/virt-fdt-build.c                 |   2 +-
 tests/data/acpi/loongarch64/virt/DSDT         | Bin 4603 -> 4379 bytes
 tests/data/acpi/loongarch64/virt/DSDT.memhp   | Bin 5824 -> 5600 bytes
 tests/data/acpi/loongarch64/virt/DSDT.numamem | Bin 4609 -> 4385 bytes
 .../data/acpi/loongarch64/virt/DSDT.topology  | Bin 4905 -> 4681 bytes
 6 files changed, 2 insertions(+), 12 deletions(-)


base-commit: 8967b2fe1b2aaae3c29e207d85fab901d580a2dc
-- 
2.56.0