hw/intc/loongarch_extioi.c | 51 ++++++++++++++++++++++++------------- hw/intc/loongarch_ipi.c | 9 ++++--- hw/intc/loongarch_pch_pic.c | 28 +++++++++++--------- 3 files changed, 55 insertions(+), 33 deletions(-)
With the clang sanitizer configured with
"--enable-ubsan --cc=clang --cxx=clang++" and run 'make check'. The
test-hmp test falls over with this backtrace:
../../hw/intc/loongarch_extioi.c:439:33: runtime error: load of
misaligned address 0x5b0a281448b4 for type 'uint64_t' (aka 'unsigned
long'), which requires 8 byte alignment.
Here LoongArch irqchip information is accessed by its natual aligned
method, and here is output of command 'info pic'
loongarch_ipi:
CPU 0 status=0x0 en=0xffffffff
MBX[6] 0x00082270
CPU 1 status=0x0 en=0xffffffff
CPU 2 status=0x0 en=0xffffffff
CPU 3 status=0x0 en=0xffffffff
loongarch_pic:
mask 0xffffffffffffff7b msi_en 0xffffffffffffffff edge 0x0000000000000080 clr 0x0000000000000000
last_irr 0x0000000000000040 irr 0x0000000000000040 isr 0x0000000000000000 polary 0x0000000000000000
MSI map:
[ 0 - 3] 0x00 0x01 0x02 0x03
...
[60 - 63] 0x3c 0x3d 0x3e 0x3f
loongarch.extioi:
ISR 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
ENABLE 0xffffffff 0xffffffff 0xffffffff 0xffffffff
0xffffffff 0xffffffff 0xffffffff 0xffffffff
IPMAP 0x02020202 0x02020202
IRQ route:
[0 - 15 ] 0x01010101 0x01010101 0x01010101 0x01010101
...
[240 - 255] 0x01010101 0x01010101 0x01010101 0x01010101
Fixes: 970657e490c0 ("hw/intc/loongarch_extioi: Add extioi interrupt status display")
Fixes: 761eb76a3bc7 ("hw/intc/loongarch_ipi: Add ipi interrupt status display")
Fixes: 82f472fa380a ("hw/intc/loongarch_pch_pic: Add pic interrupt status display")
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
hw/intc/loongarch_extioi.c | 51 ++++++++++++++++++++++++-------------
hw/intc/loongarch_ipi.c | 9 ++++---
hw/intc/loongarch_pch_pic.c | 28 +++++++++++---------
3 files changed, 55 insertions(+), 33 deletions(-)
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index 06f2aa7b14..ccc4eed199 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -425,7 +425,7 @@ static void loongarch_extioi_print_info(InterruptStatsProvider *obj,
GString *buf)
{
LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(obj);
- uint64_t *val;
+ uint32_t *val;
unsigned long irq;
ExtIOICore *core;
int i;
@@ -433,22 +433,35 @@ static void loongarch_extioi_print_info(InterruptStatsProvider *obj,
vmstate_extioi_pre_save(s);
g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj)));
- val = (uint64_t *)s->isr;
- g_string_append_printf(buf, " ISR 0x%016"PRIx64" 0x%016"PRIx64
- " 0x%016"PRIx64" 0x%016"PRIx64"\n",
+ val = s->isr;
+ g_string_append_printf(buf, " ISR 0x%08"PRIx32" 0x%08"PRIx32
+ " 0x%08"PRIx32" 0x%08"PRIx32"\n",
*val, *(val + 1), *(val + 2), *(val + 3));
- val = (uint64_t *)s->enable;
- g_string_append_printf(buf, " ENABLE 0x%016"PRIx64" 0x%016"PRIx64
- " 0x%016"PRIx64" 0x%016"PRIx64"\n",
+ val += 4;
+ g_string_append_printf(buf, " 0x%08"PRIx32" 0x%08"PRIx32
+ " 0x%08"PRIx32" 0x%08"PRIx32"\n",
+ *val, *(val + 1), *(val + 2), *(val + 3));
+ val = s->enable;
+ g_string_append_printf(buf, " ENABLE 0x%08"PRIx32" 0x%08"PRIx32
+ " 0x%08"PRIx32" 0x%08"PRIx32"\n",
+ *val, *(val + 1), *(val + 2), *(val + 3));
+ val += 4;
+ g_string_append_printf(buf, " 0x%08"PRIx32" 0x%08"PRIx32
+ " 0x%08"PRIx32" 0x%08"PRIx32"\n",
*val, *(val + 1), *(val + 2), *(val + 3));
- val = (uint64_t *)s->ipmap;
- g_string_append_printf(buf, " IPMAP 0x%016"PRIx64"\n", *val);
- val = (uint64_t *)s->coremap;
- for (i = 0; i < EXTIOI_IRQS; i += 32) {
- g_string_append_printf(buf, " COREMAP 0x%016"PRIx64" 0x%016"PRIx64
- " 0x%016"PRIx64" 0x%016"PRIx64"\n",
- *val, *(val + 1), *(val + 2), *(val + 3));
+ val = s->ipmap;
+ g_string_append_printf(buf, " IPMAP 0x%08"PRIx32" 0x%08"PRIx32"\n",
+ *val, *(val + 1));
+
+ val = s->coremap;
+ g_string_append_printf(buf, " IRQ route:\n");
+ for (i = 0; i < (EXTIOI_IRQS / 4); i += 4) {
+ g_string_append_printf(buf, " [%-3u - %-3u] 0x%08"PRIx32
+ " 0x%08"PRIx32" 0x%08"PRIx32
+ " 0x%08"PRIx32"\n",
+ i * 4, i * 4 + 15, *val, *(val + 1),
+ *(val + 2), *(val + 3));
val += 4;
}
@@ -464,11 +477,15 @@ static void loongarch_extioi_print_info(InterruptStatsProvider *obj,
continue;
}
- val = (uint64_t *)core->coreisr;
- g_string_append_printf(buf, " CPU[%d] ISR 0x%016"PRIx64" 0x%016"PRIx64
- " 0x%016"PRIx64" 0x%016"PRIx64"\n",
+ val = core->coreisr;
+ g_string_append_printf(buf, " CPU[%-3u] ISR 0x%08"PRIx32" 0x%08"PRIx32
+ " 0x%08"PRIx32" 0x%08"PRIx32"\n",
i, *val, *(val + 1), *(val + 2),
*(val + 3));
+ val += 4;
+ g_string_append_printf(buf, " 0x%08"PRIx32" 0x%08"PRIx32
+ " 0x%08"PRIx32" 0x%08"PRIx32"\n",
+ *val, *(val + 1), *(val + 2), *(val + 3));
}
}
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index c8f775a93e..7efdfc904d 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -199,7 +199,7 @@ static void loongarch_ipi_print_info(InterruptStatsProvider *obj, GString *buf)
LoongsonIPICommonState *lics = LOONGSON_IPI_COMMON(obj);
int i, j;
IPICore *core;
- uint64_t mbx;
+ uint32_t mbx;
unsigned long pos;
loongarch_ipi_pre_save(lics);
@@ -221,10 +221,11 @@ static void loongarch_ipi_print_info(InterruptStatsProvider *obj, GString *buf)
continue;
}
- for (j = 0; j < IPI_MBX_NUM; j++) {
- mbx = *(uint64_t *)&core->buf[2 * j];
+ for (j = 0; j < (IPI_MBX_NUM * 2); j++) {
+ mbx = core->buf[j];
if (mbx) {
- g_string_append_printf(buf, " MBX[%-1u] 0x%016"PRIx64, j, mbx);
+ g_string_append_printf(buf, " MBX[%-1u] 0x%08"PRIx32,
+ j, mbx);
}
}
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index 34090514ec..555575a377 100644
--- a/hw/intc/loongarch_pch_pic.c
+++ b/hw/intc/loongarch_pch_pic.c
@@ -335,7 +335,8 @@ static int loongarch_pic_post_load(LoongArchPICCommonState *opaque,
static void loongarch_pic_print_info(InterruptStatsProvider *obj, GString *buf)
{
LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(obj);
- uint64_t *vector;
+ uint8_t *vector, val;
+ int i;
loongarch_pic_pre_save(s);
g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj)));
@@ -350,17 +351,20 @@ static void loongarch_pic_print_info(InterruptStatsProvider *obj, GString *buf)
s->last_intirr, s->intirr, s->intisr,
s->int_polarity);
- vector = (uint64_t *)s->htmsi_vector;
- g_string_append_printf(buf, " MSI map 0x%016"PRIx64" 0x%016"PRIx64
- " 0x%016"PRIx64" 0x%016"PRIx64"\n",
- *vector, *(vector + 1), *(vector + 2),
- *(vector + 3));
-
- vector += 4;
- g_string_append_printf(buf, " 0x%016"PRIx64" 0x%016"PRIx64
- " 0x%016"PRIx64" 0x%016"PRIx64"\n",
- *vector, *(vector + 1), *(vector + 2),
- *(vector + 3));
+ vector = s->htmsi_vector;
+ g_string_append_printf(buf, " MSI map:\n");
+ for (i = 0; i < 64; i += 4, vector += 4) {
+ val = *vector | *(vector + 1) | *(vector + 2) | *(vector + 3);
+ /* skip zero mapping */
+ if (val == 0) {
+ continue;
+ }
+
+ g_string_append_printf(buf, " [%2d - %2d] 0x%02"PRIx8" 0x%02"PRIx8
+ " 0x%02"PRIx8" 0x%02"PRIx8"\n",
+ i, i + 3, *vector, *(vector + 1),
+ *(vector + 2), *(vector + 3));
+ }
}
static void loongarch_pic_class_init(ObjectClass *klass, const void *data)
base-commit: 8967b2fe1b2aaae3c29e207d85fab901d580a2dc
--
2.54.0On Wed, 21 Oct 2026 at 04:34, Bibo Mao <maobibo@loongson.cn> wrote:
>
> With the clang sanitizer configured with
> "--enable-ubsan --cc=clang --cxx=clang++" and run 'make check'. The
> test-hmp test falls over with this backtrace:
> ../../hw/intc/loongarch_extioi.c:439:33: runtime error: load of
> misaligned address 0x5b0a281448b4 for type 'uint64_t' (aka 'unsigned
> long'), which requires 8 byte alignment.
>
> Here LoongArch irqchip information is accessed by its natual aligned
> method, and here is output of command 'info pic'
> loongarch_ipi:
> CPU 0 status=0x0 en=0xffffffff
> MBX[6] 0x00082270
> CPU 1 status=0x0 en=0xffffffff
> CPU 2 status=0x0 en=0xffffffff
> CPU 3 status=0x0 en=0xffffffff
> loongarch_pic:
> mask 0xffffffffffffff7b msi_en 0xffffffffffffffff edge 0x0000000000000080 clr 0x0000000000000000
> last_irr 0x0000000000000040 irr 0x0000000000000040 isr 0x0000000000000000 polary 0x0000000000000000
> MSI map:
> [ 0 - 3] 0x00 0x01 0x02 0x03
> ...
> [60 - 63] 0x3c 0x3d 0x3e 0x3f
> loongarch.extioi:
> ISR 0x00000000 0x00000000 0x00000000 0x00000000
> 0x00000000 0x00000000 0x00000000 0x00000000
> ENABLE 0xffffffff 0xffffffff 0xffffffff 0xffffffff
> 0xffffffff 0xffffffff 0xffffffff 0xffffffff
> IPMAP 0x02020202 0x02020202
> IRQ route:
> [0 - 15 ] 0x01010101 0x01010101 0x01010101 0x01010101
> ...
> [240 - 255] 0x01010101 0x01010101 0x01010101 0x01010101
>
> Fixes: 970657e490c0 ("hw/intc/loongarch_extioi: Add extioi interrupt status display")
> Fixes: 761eb76a3bc7 ("hw/intc/loongarch_ipi: Add ipi interrupt status display")
> Fixes: 82f472fa380a ("hw/intc/loongarch_pch_pic: Add pic interrupt status display")
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> hw/intc/loongarch_extioi.c | 51 ++++++++++++++++++++++++-------------
> hw/intc/loongarch_ipi.c | 9 ++++---
> hw/intc/loongarch_pch_pic.c | 28 +++++++++++---------
> 3 files changed, 55 insertions(+), 33 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
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