The original patches assumed that pin had to be configured as input in
order to be able to receive interrupt. However, after additional testing
with libgpiod and gpiomon, the pin is actually supposed to be configured
as EINT (0x06). In the following example with PH1
root@cubieboard-ng:~# gpioget -c 0 224
allwinner_gpio_read [PH:CFG0] -> 0x1061061
allwinner_gpio_write [PH:CFG0] <- 0x1061060
allwinner_gpio_read [PH:DAT] -> 0x49
"224"=active
root@cubieboard-ng:~# gpiomon -c 0 224
allwinner_gpio_read [PH:CFG0] -> 0x1061060
allwinner_gpio_write [PH:CFG0] <- 0x1061066
...
The CFG0 value on the lowest nibble changes from 0 to 6.
This patch set fixes that behavior to expect that pin is configured as
EINT in order to allow interrupt-related functionality.
Tests are also updated to reflect this change, and a new test for pins
configured as input is added.
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
---
Changes in v2:
- Moved changes to the interrupt handling tests to the first commit, so
tests still pass once the commit is applied.
- Kept new GPIO input test as a separate commit.
- Link to v1: https://lore.kernel.org/qemu-devel/20261009-allwinner-gpio-eint-v1-0-c55d2958ae0b@gmail.com
---
Strahinja Jankovic (2):
hw/gpio: Add EINT CFG to Allwinner GPIO, fix interrupt handling
tests/qtest: Add Allwinner GPIO input test
hw/gpio/allwinner-gpio.c | 19 +++++++++---
include/hw/gpio/allwinner-gpio-regs.h | 5 +--
tests/qtest/allwinner-gpio-test.c | 57 ++++++++++++++++++++++++++---------
3 files changed, 57 insertions(+), 24 deletions(-)
---
base-commit: a19f59a72d96056d9a8f48cf6c77f5787491e414
change-id: 20261009-allwinner-gpio-eint-1818f24ae7d5
Best regards,
--
Strahinja Jankovic <strahinja.p.jankovic@gmail.com>