[v1] RISC-V: ACPI: Add PPTT support

[PATCH 0/4] RISC-V: ACPI: Add PPTT support

Sunil V L via qemu development posted 4 patches 1 week, 4 days ago

Diff against v2
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MAINTAINERS                       |   2 +-
hw/riscv/virt-acpi-build.c        |   7 ++++
hw/riscv/virt.c                   |  54 ++++++++++++++++++++++++++++++
include/hw/riscv/virt.h           |   4 +++
tests/data/acpi/riscv64/virt/PPTT | Bin 0 -> 96 bytes
5 files changed, 66 insertions(+), 1 deletion(-)
create mode 100644 tests/data/acpi/riscv64/virt/PPTT

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[PATCH 0/4] RISC-V: ACPI: Add PPTT support

Posted by Sunil V L via qemu development 1 week, 4 days ago

From: Sunil V L <sunilvl@oss.qualcomm.com>

Hi all,

This series adds ACPI Processor Properties Topology Table (PPTT) support to
the RISC-V virt machine. PPTT allows the guest to discover the processor and
cache topology exposed by the machine, which is useful for making better
scheduling and cache-management decisions.

The implementation describes the RISC-V virt cache hierarchy with separate
L1 instruction and data caches, followed by unified L2 and L3 caches. It also
enables the corresponding cache and cluster properties in the machine SMP
description and wires the generated PPTT into the existing ACPI table
build.

Unlike ARM, RISC-V doesn't have a way to discover the Cache
topology from registers. Hence, I am hardcoding default values for the
cache topology structures. These cache topology structures are added in
virt.c itself so that a future series can add support for DT as well.

The series also updates the bios-tables-test data and removes the temporary
PPTT entry from the allowed-diff list. The generated table is 96 bytes and
describes the package, cluster, and processor hierarchy for the virt machine.

This work follows the discussion and earlier work shared here:
https://lists.gnu.org/archive/html/qemu-riscv/2024-01/msg00928.html

I have retained the contribution from Sia Jee Heng and added his
Signed-off-by tag to the relevant patch.

To enable cache structures in the PPTT, one should use similar to below
command line option.

-M virt,smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core,smp-cache.2.cache=l2,smp-cache.2.topology=cluster,smp-cache.3.cache=l3,smp-cache.3.topology=socket

lscpu -C in linux can be used to display these cache structures.

Sunil V L (4):
  tests/qtest/bios-tables-test: Allow PPTT for RISC-V
  hw/riscv/virt: Add ACPI PPTT table
  tests/qtest/bios-tables-test: Update riscv64 virt PPTT golden
    reference
  MAINTAINERS: Update Sunil's email id

 MAINTAINERS                       |   2 +-
 hw/riscv/virt-acpi-build.c        |   7 ++++
 hw/riscv/virt.c                   |  54 ++++++++++++++++++++++++++++++
 include/hw/riscv/virt.h           |   4 +++
 tests/data/acpi/riscv64/virt/PPTT | Bin 0 -> 96 bytes
 5 files changed, 66 insertions(+), 1 deletion(-)
 create mode 100644 tests/data/acpi/riscv64/virt/PPTT

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