[PATCH v2 00/18] single-binary: target/riscv, compile subset of compilation units once

Anton Johansson via qemu development posted 18 patches 2 weeks, 2 days ago
target/riscv/internals.h            |  31 +-
target/riscv/tcg/csr.h              |  37 +-
target/riscv/tcg/debug.h            |  11 +-
target/riscv/tcg/pmu.h              |   3 -
target/riscv/tcg/vector_internals.h |   5 +-
target/riscv/arch_dump.c            |  13 +-
target/riscv/cpu.c                  | 255 ++++++++-----
target/riscv/gdbstub.c              |   2 +-
target/riscv/kvm/kvm-stub.c         |  21 +
target/riscv/machine.c              |  10 +-
target/riscv/monitor.c              |  91 +++--
target/riscv/tcg/cpu_helper.c       |  79 ++--
target/riscv/tcg/csr.c              | 736 ++++++++++++++++++------------------
target/riscv/tcg/debug.c            | 150 ++++----
target/riscv/tcg/mips_csr.c         |  12 +-
target/riscv/tcg/op_helper.c        |   6 +-
target/riscv/tcg/pmp.c              |  19 +-
target/riscv/tcg/pmu.c              |   9 +-
target/riscv/tcg/tcg-cpu.c          |   8 +-
target/riscv/tcg/th_csr.c           |   6 +-
target/riscv/tcg/vector_helper.c    |  64 ++--
target/riscv/meson.build            |  18 +-
target/riscv/tcg/meson.build        |  21 +-
23 files changed, 847 insertions(+), 760 deletions(-)
[PATCH v2 00/18] single-binary: target/riscv, compile subset of compilation units once
Posted by Anton Johansson via qemu development 2 weeks, 2 days ago
All compilation units which do not pull in helper definitions are
compiled once for system mode by widening target_ulong to
uint64_t.

This series is motivated by the fact that riscv64 already handles
XLEN == 32 as a subset of the 64-bit ISA.  As such we can reduce
duplicate compilation units by moving towards riscv64 as default.

If anyone more familiar with riscv is aware of differences between XLEN
== 32 on riscv64 vs riscv32, please do let me know. No behaviour change
is intended compared to riscv32.

Based on: 20260916-hw-riscv-cpu-int-v4-0-babc367b60f5@rev.ng

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
Changes in v2:
- Define BARE/MAX cpus using separate tables indexed by
  target_riscv64(), similar to arm.
- Moved monitor.c HMP field formatting to printf specifiers to retain
  field widths (Philippe).
- Link to v1: https://lore.kernel.org/qemu-devel/20261001-rv-dedup-v1-0-ea69b07afd31@rev.ng

---
Anton Johansson (18):
      target/riscv: Make internals.h target agnostic
      target/riscv: meson, add user and common system source sets
      target/riscv: Move pmu CSR read to csr.h
      target/riscv: Make debug.c target agnostic
      target/riscv: Widen CSR ops to 64-bit and compile once for system-mode
      target/riscv: Runtime CPU registration
      target/riscv: Runtime register MAX and BARE CPUs
      target/riscv: cpu.c unconditionally check larger MXL
      target/riscv: Stub KVM functions for machines.c/cpu.c
      target/riscv: Compile cpu.c once for system-mode
      target/riscv: Compile cpu_helper.c once for system-mode
      target/riscv: Compile tcg-cpu.c once for system-mode
      target/riscv: Compile riscv-qmp-cmds.c once
      target/riscv: Compile pmp.c once
      target/riscv: Compile arch_dump.c once
      target/riscv: Compile machine.c once
      target/riscv: Compile time_helper.c once
      target/riscv: Compile monitor.c once

 target/riscv/internals.h            |  31 +-
 target/riscv/tcg/csr.h              |  37 +-
 target/riscv/tcg/debug.h            |  11 +-
 target/riscv/tcg/pmu.h              |   3 -
 target/riscv/tcg/vector_internals.h |   5 +-
 target/riscv/arch_dump.c            |  13 +-
 target/riscv/cpu.c                  | 255 ++++++++-----
 target/riscv/gdbstub.c              |   2 +-
 target/riscv/kvm/kvm-stub.c         |  21 +
 target/riscv/machine.c              |  10 +-
 target/riscv/monitor.c              |  91 +++--
 target/riscv/tcg/cpu_helper.c       |  79 ++--
 target/riscv/tcg/csr.c              | 736 ++++++++++++++++++------------------
 target/riscv/tcg/debug.c            | 150 ++++----
 target/riscv/tcg/mips_csr.c         |  12 +-
 target/riscv/tcg/op_helper.c        |   6 +-
 target/riscv/tcg/pmp.c              |  19 +-
 target/riscv/tcg/pmu.c              |   9 +-
 target/riscv/tcg/tcg-cpu.c          |   8 +-
 target/riscv/tcg/th_csr.c           |   6 +-
 target/riscv/tcg/vector_helper.c    |  64 ++--
 target/riscv/meson.build            |  18 +-
 target/riscv/tcg/meson.build        |  21 +-
 23 files changed, 847 insertions(+), 760 deletions(-)