Hi All,
Here is v4 of the RFC for named CPU models on Arm64/KVM.
Background:
=============================================================
Currently QEMU only supports -cpu host/max for KVM on Arm64. This blocks
live migration of VMs between hosts that differ in CPU features.
This RFC proposes hierarchical named models for Arm64 under KVM. A named
model is a strict contract of the CPU features exposed to the guest, so
the same model resolves to the same guest-visible ID registers on any
capable host. Models can be customized further by overriding individual
ID-register fields (e.g. SYSREG_ID_AA64ISAR0_EL1_SHA1=0).
On top of the models, this series adds the QMP introspection support on
Arm that the management layer already depends on for x86:
`query-cpu-definitions` lists the models a host can run and reports
blockers for the ones it cannot, `query-cpu-model-expansion` resolves a
model to its full set of properties, and the new `query-cpu-props-info`
reports the values the host supports for each property. The aim is feature
parity with x86 so existing tooling can consume Arm named models with
little change.
TL;DR examples:
=============================================================
# Boot a named model
qemu-system-aarch64 -cpu grace-v1 -machine virt,accel=kvm ...
# Named model with ID-register field override
qemu-system-aarch64 -cpu grace-v1,SYSREG_ID_AA64ISAR0_EL1_SHA1=0 ...
# -cpu host with ID-register field override
qemu-system-aarch64 -cpu host,SYSREG_ID_AA64ISAR0_EL1_AES=1 ...
# query-cpu-model-expansion
"model": {
"name": "graviton4-v1",
"props": {
"SYSREG_ID_AA64ISAR0_EL1_AES": 2,
"SYSREG_ID_AA64ISAR0_EL1_SHA1": 1,
"SYSREG_ID_AA64ISAR0_EL1_SHA2": 2,
"SYSREG_ID_AA64ISAR1_EL1_APA": 3,
"SYSREG_ID_AA64PFR0_EL1_SVE": 1,
"sve": true,
"sve128": true,
...
}
}
# query-cpu-definitions: blockers reporting
{
"name": "graviton4-v1",
"typename": "graviton4-v1-arm-cpu",
"unavailable-features": [
"SYSREG_ID_AA64MMFR0_EL1_TGran16_2",
"SYSREG_ID_AA64MMFR0_EL1_TGran64_2",
"SYSREG_ID_AA64MMFR0_EL1_TGran4_2",
"SYSREG_ID_AA64ISAR1_EL1_APA",
"SYSREG_ID_AA64ISAR0_EL1_SM3",
"SYSREG_ID_AA64ISAR0_EL1_SM4"
],
"static": false,
"deprecated": false
}
# new query-cpu-props-info: supported values per property
{
"name": "SYSREG_ID_AA64ISAR0_EL1_AES",
"supported-values": [
{ "min": 2, "max": 2 },
{ "min": 1, "max": 1 },
{ "min": 0, "max": 0 }
],
"type": "number"
},
{
"name": "sve",
"supported-values": [ true, false ],
"type": "boolean"
}
The series can be found at:
https://github.com/khushit-shah-nx/qemu/tree/rfc-v4
Changes from v3 -> v4:
- Rebased on v8 of Eric Auger's customizable AArch64 KVM host-model
series.
- Stopped exposing reserved ID-register fields, as suggested by Eric.
- Converted appropriate warnings to trace events, as suggested by Eric.
- Split the per-field ID-register writeback refactoring from the
special-field handling.
- Each model now has a separate patch containing its final ID-register
state and architecture references, as suggested by Eric.
- Removed the non-zero-defaults named model layer, as suggested by Eric.
- Disabled PMU for named models.
- Added forward-compatibility: reject a named model when KVM exposes an
unknown feature ID register with a non-zero value.
- Split query-cpu-props-info's generic QAPI definition and its
Arm/KVM implementation.
- Moved query-cpu-definitions ID-register blocker calculation from
generic Arm code into the KVM-specific implementation.
- Dropped the narrow EL2 writeback workaround; this is now handled
properly by Eric's v9 series.
v3: https://lore.kernel.org/qemu-arm/20260716213858.609699-1-khushit.shah@nutanix.com/
Left out:
- CNTFRQ_EL0 handling during heterogenous migrations: This is not related
to named CPU models, will send separate patch for this.
- SYSREG_ prop and legacy prop interaction/consistency: handled by Eric
Khushit Shah (25):
target/arm: expose SYSREG_ props for REVIDR_EL1 and AIDR_EL1
target/arm: expose all non-res ID reg fields as properties
target/arm: move SYSREG_ prop infra to cpu64.c
target/arm/kvm: enable writable implementation ID registers
target/arm/kvm: read all ID registers from KVM
target/arm/kvm: handle special ID registers when reading from KVM
target/arm/kvm: process ID register writeback per field
target/arm/kvm: handle writeback for special ID register fields
target/arm: introduce named CPU model infrastructure
target/arm: fix SVE and PAuth finalize for named CPU models
target/arm: disable PMU support for named CPU models
target/arm: add arm-v9.0-a-v1 named CPU model
target/arm: add neoverse-v2-v1 named CPU model
target/arm: add neoverse-v2-v2 named CPU model
target/arm: add graviton4-v1 named CPU model
target/arm: add grace-v1 named CPU model
target/arm: fail named CPU models on unknown non-zero feature ID regs
target/arm: add cpu-models-stub.c
target/arm/qmp: allow named CPU models on cpu-model-expansion
target/arm/kvm: compute host-supported values for ID register fields
target/arm: report 0 as supported for ID fields gated by vCPU init
flags
target/arm/kvm: add kvm_arm_get_host_isar helper
qmp: add query-cpu-props-info command
target/arm/qmp: implement query-cpu-props-info for KVM
target/arm/qmp: hook blockers in query-cpu-definitions
docs/system/arm/cpu-features.rst | 34 +-
hw/arm/virt.c | 7 +
qapi/machine.json | 82 +++
.../update-aarch64-cpu-sysreg-properties.py | 9 +
stubs/meson.build | 1 +
stubs/qmp-cpu-props-info.c | 12 +
target/arm/arm-qmp-cmds.c | 105 ++++
target/arm/cpu-idregs.c | 19 +
target/arm/cpu-idregs.h | 4 +
target/arm/cpu-idregs.h.inc | 2 +
target/arm/cpu-models-stub.c | 18 +
target/arm/cpu-models.c | 536 ++++++++++++++++++
target/arm/cpu-models.h | 38 ++
target/arm/cpu-sysregs.h | 2 +-
target/arm/cpu64.c | 139 ++++-
target/arm/internals.h | 1 +
target/arm/kvm-stub.c | 19 +
target/arm/kvm.c | 521 +++++++++++------
target/arm/kvm_arm.h | 57 +-
target/arm/meson.build | 2 +
target/arm/trace-events | 9 +-
tests/qtest/qmp-cmd-test.c | 1 +
22 files changed, 1404 insertions(+), 214 deletions(-)
create mode 100644 stubs/qmp-cpu-props-info.c
create mode 100644 target/arm/cpu-models-stub.c
create mode 100644 target/arm/cpu-models.c
create mode 100644 target/arm/cpu-models.h
--
2.52.0