This series enhances the current host KVM model with capability to
set writable ID reg fields.
Since v6.7 kernel, KVM/arm allows the userspace to overwrite the values
of a subset of ID regs. The list of writable fields continues to grow.
The feature ID range is defined as the AArch64 System register space
with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}.
The end goal is to get more flexibility when migrating guests
between different host hardware.
QEMU retrieves the writable ID fields from KVM UAPI and
match them against a generated description of ID regs and their
named fields that stem from AARCHMRS Registers.json file.
Current description is based on latest 2026-03 edition.
The content of the generated files was compared against kernel
linux/arch/arm64/tools/sysreg file. It is not straightforward
to have unit tests for python scripts as there are many cases for
field extraction.
For each writable named field a uint64 property is created
following the "SYSREG_<REG>_<FIELD>" naming convention. REG and
FIELD names are those described in ARM ARM Reference manual.
SYSREG properties are applied at the end of the initialization
chain, after legacy composite options (sve, pauth, ...). They
do not substitute to them because legacy options do more than
just changing the value of ID registers. They may also interact
with KVM to init the vcpu with specific features or set some
VM capabilities. SYSREG properties just affect the corresponding
ID register field. Some checks are performed to make sure their
value is not inconsistent with legacy composite options.
The list of SYSREG properties can be retrieved through the qmp
monitor using query-cpu-model-expansion. They return the current
value for the corresponding field. The qmp command also allows to
test setting new values. In static mode, they are tested at qemu
level only, against field length, arch enum values if any and
consistency with legacy composite options. With full expansion,
the values are tested against KVM using a scratch vcpu initialized
with the right legacy composite property values.
Connie & Eric
This series can be found at:
https://github.com/eauger/qemu/tree/arm-cpu-model-v9
History:
--------
v8 -> v9:
- Eventually turned this series into non RFC series as main
blockers have been removed I think
- Changed the way SYSREG props are applied, first stored into
a hashkey and applied at the very end of the init chain, after
legacy composite options. This fixes the issue with NV.
- Also we are running the expansion code on a scratch vcpu mode
that should be similar to the final one, initialized with the
right composite options.
- Introduced the static support for expansion. In static mode,
we don't run checks against the scratch vcpu
- Added consistency checks between legacy composite options and
SYSREG props
- Addressed the 2 bugs reported by Khushit & Shameer (scrach vcpu
leak in expansion code and RES field handling)
- pass errp to kvm_arch_init_vcpu()
- introduced kvm_arm_vcpu_prepare_init_features
Cornelia Huck (3):
target/arm/kvm: Retrieve writable ID reg map
arm-qmp-cmds: introspection for ID register props
arm/cpu-features: document ID reg properties
Eric Auger (22):
scripts: introduce scripts/update-aarch64-cpu-sysregs-header.py
target/arm/cpu-sysregs.h.inc: Sort by name alphabetical order
target/arm/cpu-sysregs.h.inc: Update with automatic generation
arm/cpu: Add infra to handle generated ID register definitions
scripts: Introduce scripts/aarch64_sysreg_helpers module
scripts: Introduce scripts/update-aarch64-cpu-sysreg-properties.py
target/arm/cpu-idregs.h.inc: generate with script
target/arm/cpu-idregs.h.inc: Generate enum values
hw/arm/virt: Make sure virt_get_caches() keeps on reading CLIDR_EL1 as
0
arm/kvm: Initialize isar.idregs[] with all writable host ID regs
target/arm/kvm: Introduce kvm_arm_expose_idreg_properties
target/arm/kvm: Implement SYSREG property setter and getter
target/arm/kvm: Pass an Error handle to kvm_arch_init_vcpu
target/arm/kvm: Apply SYSREG props to the final vcpu
target/arm/kvm: Add consistency checking for SYSREG props
target/arm/cpu: Expose writable ID reg field properties on the kvm
host vcpu model
target/arm/cpu-idregs.h.inc: Generate reserved fields
target/arm/kvm: Ignore and trace unexpected writable reserved fields
target/arm/kvm: add helper to test SYSREG props against a scratch vcpu
target/arm/kvm: Add an error handle to
kvm_arm_create_scratch_host_vcpu
target/arm/kvm: Introduce kvm_arm_vcpu_prepare_init_features helper
target/arm/kvm: Introduce kvm_arm_create_init_scratch_vcpu()
Shaju Abraham (1):
target/arm/cpu_idregs: generate tables for Arm64 ID registers and
fields
docs/system/arm/cpu-features.rst | 100 +-
include/system/kvm.h | 2 +-
target/arm/cpu-idregs.h | 36 +
target/arm/cpu.h | 2 +
target/arm/kvm_arm.h | 28 +-
target/arm/cpu-idregs.h.inc | 2512 +++++++++++++++++
target/arm/cpu-sysregs.h.inc | 55 +-
accel/kvm/kvm-all.c | 15 +-
hw/arm/virt.c | 4 +
target/arm/arm-qmp-cmds.c | 107 +-
target/arm/cpu-idregs.c | 96 +
target/arm/cpu.c | 5 +-
target/arm/cpu64.c | 5 +
target/arm/kvm-stub.c | 17 +
target/arm/kvm.c | 560 +++-
target/i386/kvm/kvm.c | 22 +-
target/loongarch/kvm/kvm.c | 24 +-
target/ppc/kvm.c | 6 +-
target/riscv/kvm/kvm-cpu.c | 3 +-
target/s390x/kvm/kvm.c | 2 +-
scripts/aarch64_sysreg_helpers.py | 121 +
.../update-aarch64-cpu-sysreg-properties.py | 299 ++
scripts/update-aarch64-cpu-sysregs-header.py | 51 +
target/arm/meson.build | 1 +
target/arm/trace-events | 9 +
25 files changed, 3987 insertions(+), 95 deletions(-)
create mode 100644 target/arm/cpu-idregs.h
create mode 100644 target/arm/cpu-idregs.h.inc
create mode 100644 target/arm/cpu-idregs.c
create mode 100644 scripts/aarch64_sysreg_helpers.py
create mode 100644 scripts/update-aarch64-cpu-sysreg-properties.py
create mode 100755 scripts/update-aarch64-cpu-sysregs-header.py
--
2.53.0