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[PULL 00/20] target-arm queue

Peter Maydell posted 20 patches 1 week, 4 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260915170735.425445-1-peter.maydell@linaro.org
Maintainers: Samuel Tardieu <sam@rfc1149.net>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>, Leif Lindholm <leif.lindholm@oss.qualcomm.com>, Alexander Graf <agraf@csgraf.de>, Pedro Barbuda <pbarbuda@microsoft.com>, Mohamed Mediouni <mohamed@unpredictable.fr>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>
There is a newer version of this series
MAINTAINERS                             |   4 +-
hw/char/stm32l4x5_usart.c               |   1 +
hw/intc/armv7m_nvic.c                   |  42 +++++-
hw/intc/bcm2835_ic.c                    |  13 +-
hw/misc/bcm2835_powermgt.c              |   8 +
hw/watchdog/sbsa_gwdt.c                 |  87 +++++++----
target/arm/cpu.c                        |  12 +-
target/arm/hvf/hvf.c                    |  10 ++
target/arm/machine.c                    |   3 +-
target/arm/ptw.c                        |  14 +-
target/arm/tcg/cpu32.c                  |   1 +
target/arm/whpx/whpx-all.c              | 254 ++++++++++++++++++--------------
tests/qtest/bcm2835-ic-test.c           |  66 +++++++++
tests/qtest/meson.build                 |   2 +-
tests/tcg/arm/system/meson.build        |   6 +
tests/tcg/arm/system/test-armv6m-nvic.S |  70 +++++++++
16 files changed, 439 insertions(+), 154 deletions(-)
create mode 100644 tests/qtest/bcm2835-ic-test.c
create mode 100644 tests/tcg/arm/system/test-armv6m-nvic.S
[PULL 00/20] target-arm queue
Posted by Peter Maydell 1 week, 4 days ago 
Hi; here's an arm pullreq; pretty much all bugfixes this time.

thanks
-- PMM

The following changes since commit 5f664cd37aec17e8145aa117d8da68f507edc8f1:

  Merge tag 'ui-pr-v1' of https://gitlab.com/marcandre.lureau/qemu into staging (2026-09-13 15:54:17 -1000)

are available in the Git repository at:

  https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20260915

for you to fetch changes up to 157f6c69edd0627f5f78f1f14ea0d831b0948c69:

  target/arm: extend PMSAv7 support to v6-M CPUs (2026-09-15 14:27:23 +0100)

----------------------------------------------------------------
target-arm queue:
 * target/arm/whpx: fix whpx-arm post-reset CPU state
 * target/arm/whpx: incorrect ENCODE_AA64_CP_REG parameter order
 * target/arm/whpx: Don't try to sync ARM_CP_CONST registers
 * hw/intc/bcm2835_ic: reject out-of-range FIQ source values
 * sbsa-gwdt: reschedule timer on direct WCV load
 * target/arm/hvf: implement MDCCSR_EL0 as RAZ
 * hw/char/stm32l4x5_usart: Accept character input upon RDR read
 * MAINTAINERS: Update email address for Vikram Garhwal
 * hw/misc/bcm2835_powermgt: free wdog timer on finalize
 * target/arm: initialize SCTLR reset value for arm11mpcore
 * target/arm: Fix various v6M corner-case bugs

----------------------------------------------------------------
Alex Bennée (1):
      hw/char/stm32l4x5_usart: Accept character input upon RDR read

Bin Guo (1):
      hw/intc/bcm2835_ic: reject out-of-range FIQ source values

Doug Cook (3):
      target/arm/whpx: Don't try to sync ARM_CP_CONST registers
      target/arm/whpx: incorrect ENCODE_AA64_CP_REG parameter order
      target/arm/whpx: fix whpx-arm post-reset CPU state

Gilles Grimaud (5):
      target/arm: enforce Armv6-M NVIC limits
      target/arm: MPU - limit regs RBAR/RASR A1-A3 to Main Extension
      target/arm: MPU_RASR: mask TEX bits for Armv6-M
      target/arm: fix MPU SIZE min for v6-M/v7-M/v7-R
      target/arm: extend PMSAv7 support to v6-M CPUs

Igor Mammedov (6):
      sbsa-gwdt: reduce code indent
      arm: gwdt: consolidate clear WS0 and WS1 on explicit refresh
      arm: gwdt: simplify WCV update condition
      sbsa-gwdt: rename sbsa_gwdt_update_timer() to sbsa_gwdt_wor_update_timer()
      sbsa-gwdt: don't arm timer for compare values above INT64_MAX
      sbsa-gwdt: reschedule timer on direct WCV load

Marc-André Lureau (1):
      hw/misc/bcm2835_powermgt: free wdog timer on finalize

Showta Ishizaki (1):
      target/arm/hvf: implement MDCCSR_EL0 as RAZ

Vikram Garhwal (1):
      MAINTAINERS: Update email address for Vikram Garhwal

vpyr (1):
      target/arm: initialize SCTLR reset value for arm11mpcore

 MAINTAINERS                             |   4 +-
 hw/char/stm32l4x5_usart.c               |   1 +
 hw/intc/armv7m_nvic.c                   |  42 +++++-
 hw/intc/bcm2835_ic.c                    |  13 +-
 hw/misc/bcm2835_powermgt.c              |   8 +
 hw/watchdog/sbsa_gwdt.c                 |  87 +++++++----
 target/arm/cpu.c                        |  12 +-
 target/arm/hvf/hvf.c                    |  10 ++
 target/arm/machine.c                    |   3 +-
 target/arm/ptw.c                        |  14 +-
 target/arm/tcg/cpu32.c                  |   1 +
 target/arm/whpx/whpx-all.c              | 254 ++++++++++++++++++--------------
 tests/qtest/bcm2835-ic-test.c           |  66 +++++++++
 tests/qtest/meson.build                 |   2 +-
 tests/tcg/arm/system/meson.build        |   6 +
 tests/tcg/arm/system/test-armv6m-nvic.S |  70 +++++++++
 16 files changed, 439 insertions(+), 154 deletions(-)
 create mode 100644 tests/qtest/bcm2835-ic-test.c
 create mode 100644 tests/tcg/arm/system/test-armv6m-nvic.S
Re: [PULL 00/20] target-arm queue
Posted by Richard Henderson 1 week, 3 days ago 
On 9/15/26 07:07, Peter Maydell wrote:
> Hi; here's an arm pullreq; pretty much all bugfixes this time.
> 
> thanks
> -- PMM
> 
> The following changes since commit 5f664cd37aec17e8145aa117d8da68f507edc8f1:
> 
>    Merge tag 'ui-pr-v1' ofhttps://gitlab.com/marcandre.lureau/qemu into staging (2026-09-13 15:54:17 -1000)
> 
> are available in the Git repository at:
> 
>    https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20260915
> 
> for you to fetch changes up to 157f6c69edd0627f5f78f1f14ea0d831b0948c69:
> 
>    target/arm: extend PMSAv7 support to v6-M CPUs (2026-09-15 14:27:23 +0100)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * target/arm/whpx: fix whpx-arm post-reset CPU state
>   * target/arm/whpx: incorrect ENCODE_AA64_CP_REG parameter order
>   * target/arm/whpx: Don't try to sync ARM_CP_CONST registers
>   * hw/intc/bcm2835_ic: reject out-of-range FIQ source values
>   * sbsa-gwdt: reschedule timer on direct WCV load
>   * target/arm/hvf: implement MDCCSR_EL0 as RAZ
>   * hw/char/stm32l4x5_usart: Accept character input upon RDR read
>   * MAINTAINERS: Update email address for Vikram Garhwal
>   * hw/misc/bcm2835_powermgt: free wdog timer on finalize
>   * target/arm: initialize SCTLR reset value for arm11mpcore
>   * target/arm: Fix various v6M corner-case bugs

Applied, thanks.

r~

Patchew 2.1-devel-ea86937

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