[PATCH v3 00/10] Hexagon (target/hexagon) Check for multiwrites in analyze_packet

Taylor Simpson posted 10 patches 1 week, 4 days ago
Maintainers: Brian Cain <brian.cain@oss.qualcomm.com>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
target/hexagon/insn.h               |   4 -
target/hexagon/translate.h          |  47 +++++++--
target/hexagon/decode.c             |  54 ----------
target/hexagon/translate.c          |  90 +++++++++++++----
tests/tcg/hexagon/multiple-writes.c | 149 ++++++++++++++++++++++++++++
target/hexagon/gen_trans_funcs.py   |  10 --
tests/tcg/hexagon/meson.build       |   2 +-
7 files changed, 261 insertions(+), 95 deletions(-)
[PATCH v3 00/10] Hexagon (target/hexagon) Check for multiwrites in analyze_packet
Posted by Taylor Simpson 1 week, 4 days ago
Currently, we check for register multiwrites during packet decode. The
downside of this approach is that it only checks a single destination
register for each instruction.  During analyze_packet, we can check
for more than one write per instruction.  Further, we can check for
different types of registers.  This series adds checks for HVX
v-registers and q-registers.

Note that multiple writes to a predicate register are allowed on Hexagon.

Changes in v2
- Rebase against latest sources, including Hexagon system mode
- Add checks for multiple writes to system registers

Changes in v3
- Address feedback from Brian Cain <brian.cain@oss.qualcomm.com>
    Fix check-functional failures
    Typo in commit comment
- Address feedback from Marco Liebel <marco.liebel@oss.qualcomm.com>
    Add test for mixed predicated/unconditional writes to vreg


Taylor Simpson (10):
  Hexagon (target/hexagon) Move code out of gen_start_packet
  Hexagon (target/hexagon) Check for GPR multiwrite in analyze_packet
  Hexagon (tests/tcg/hexagon) Add tests for multi-destination
    instructions
  Hexagon (target/hexagon) Check for vreg multiwrite in analyze_packet
  Hexagon (tests/tcg/hexagon) Add tests for vreg multiple writes
  Hexagon (target/hexagon) Check for qreg multiwrite in analyze_packet
  Hexagon (tests/tcg/hexagon) Add tests for qreg multiple writes
  Hexagon (target/hexagon) Check for greg multiwrite in analyze_packet
  Hexagon (target/hexagon) Check for sreg multiwrite in analyze_packet
  Hexagon (target/hexagon) Remove old way of detecting register
    multiwrites

 target/hexagon/insn.h               |   4 -
 target/hexagon/translate.h          |  47 +++++++--
 target/hexagon/decode.c             |  54 ----------
 target/hexagon/translate.c          |  90 +++++++++++++----
 tests/tcg/hexagon/multiple-writes.c | 149 ++++++++++++++++++++++++++++
 target/hexagon/gen_trans_funcs.py   |  10 --
 tests/tcg/hexagon/meson.build       |   2 +-
 7 files changed, 261 insertions(+), 95 deletions(-)

-- 
2.43.0
Re: [PATCH v3 00/10] Hexagon (target/hexagon) Check for multiwrites in analyze_packet
Posted by Brian Cain 1 week, 4 days ago
On 9/14/2026 4:50 PM, Taylor Simpson wrote:
> Currently, we check for register multiwrites during packet decode. The
> downside of this approach is that it only checks a single destination
> register for each instruction.  During analyze_packet, we can check
> for more than one write per instruction.  Further, we can check for
> different types of registers.  This series adds checks for HVX
> v-registers and q-registers.
>
> Note that multiple writes to a predicate register are allowed on Hexagon.

This series is now queued for inclusion in an upcoming pull req - 
thanks, Taylor!


> Changes in v2
> - Rebase against latest sources, including Hexagon system mode
> - Add checks for multiple writes to system registers
>
> Changes in v3
> - Address feedback from Brian Cain <brian.cain@oss.qualcomm.com>
>      Fix check-functional failures
>      Typo in commit comment
> - Address feedback from Marco Liebel <marco.liebel@oss.qualcomm.com>
>      Add test for mixed predicated/unconditional writes to vreg
>
>
> Taylor Simpson (10):
>    Hexagon (target/hexagon) Move code out of gen_start_packet
>    Hexagon (target/hexagon) Check for GPR multiwrite in analyze_packet
>    Hexagon (tests/tcg/hexagon) Add tests for multi-destination
>      instructions
>    Hexagon (target/hexagon) Check for vreg multiwrite in analyze_packet
>    Hexagon (tests/tcg/hexagon) Add tests for vreg multiple writes
>    Hexagon (target/hexagon) Check for qreg multiwrite in analyze_packet
>    Hexagon (tests/tcg/hexagon) Add tests for qreg multiple writes
>    Hexagon (target/hexagon) Check for greg multiwrite in analyze_packet
>    Hexagon (target/hexagon) Check for sreg multiwrite in analyze_packet
>    Hexagon (target/hexagon) Remove old way of detecting register
>      multiwrites
>
>   target/hexagon/insn.h               |   4 -
>   target/hexagon/translate.h          |  47 +++++++--
>   target/hexagon/decode.c             |  54 ----------
>   target/hexagon/translate.c          |  90 +++++++++++++----
>   tests/tcg/hexagon/multiple-writes.c | 149 ++++++++++++++++++++++++++++
>   target/hexagon/gen_trans_funcs.py   |  10 --
>   tests/tcg/hexagon/meson.build       |   2 +-
>   7 files changed, 261 insertions(+), 95 deletions(-)
>