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[PATCH v3] target/riscv/tcg: svinval instructions raise virtual instruction

Christian S. Lima posted 1 patch 2 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260911201323.37757-1-christianslima@proton.me
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>
target/riscv/tcg/insn_trans/trans_svinval.c.inc |  3 +++
target/riscv/tcg/insn_trans/trans_xthead.c.inc  | 12 +++++++-----
2 files changed, 10 insertions(+), 5 deletions(-)
[PATCH v3] target/riscv/tcg: svinval instructions raise virtual instruction
Posted by Christian S. Lima 2 weeks ago 
The risc v privileged specification requires hinval.vvma, hinval.gvma,
sfence.w.inval and sfence.inval.ir should raise a virtual instruction
exception when executed in the vu-mode. This patch add the check to
raise the virtual instruction exception when is in the vu-mode.

changes in v3:
- Add missing semicolon

changes in v2:
- Remove the wrong `return true;` from macro

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621

Signed-off-by: Christian S. Lima <christianslima@proton.me>
---
 target/riscv/tcg/insn_trans/trans_svinval.c.inc |  3 +++
 target/riscv/tcg/insn_trans/trans_xthead.c.inc  | 12 +++++++-----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
index 4614c1489c..1341beba2f 100644
--- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
@@ -25,6 +25,9 @@
 /* Test if priv level is M or S. */
 #define REQUIRE_PRIV_MS(ctx) do {          \
     if (ctx->priv == PRV_U) {              \
+        if (ctx->virt_enabled) {           \
+            ctx->virt_inst_excp = true;    \
+        }                                  \
         return false;                      \
     }                                      \
 } while (0)
diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
index f4e3051000..ea4b169422 100644
--- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
@@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
 #define REQUIRE_PRIV_MSU(ctx)
 
 /* Test if priv level is M or S. */
-#define REQUIRE_PRIV_MS(ctx)                                    \
-do {                                                            \
-    if (ctx->priv == PRV_U) {                                   \
-        return false;                                           \
-    }                                                           \
+#define REQUIRE_PRIV_MS(ctx) do {          \
+    if (ctx->priv == PRV_U) {              \
+        if (ctx->virt_enabled) {           \
+            ctx->virt_inst_excp = true;    \
+        }                                  \
+        return false;                      \
+    }                                      \
 } while (0)
 
 #define NOP_PRIVCHECK(insn, extcheck, privcheck)                \
-- 
2.55.0
Re: [PATCH v3] target/riscv/tcg: svinval instructions raise virtual instruction
Posted by Alistair Francis 4 days, 17 hours ago 
On Fri, 2026-09-11 at 20:13 +0000, Christian S. Lima wrote:
> The risc v privileged specification requires hinval.vvma,
> hinval.gvma,
> sfence.w.inval and sfence.inval.ir should raise a virtual instruction
> exception when executed in the vu-mode. This patch add the check to
> raise the virtual instruction exception when is in the vu-mode.
> 
> changes in v3:
> - Add missing semicolon
> 
> changes in v2:
> - Remove the wrong `return true;` from macro
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621
> 
> Signed-off-by: Christian S. Lima <christianslima@proton.me>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/tcg/insn_trans/trans_svinval.c.inc |  3 +++
>  target/riscv/tcg/insn_trans/trans_xthead.c.inc  | 12 +++++++-----
>  2 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> index 4614c1489c..1341beba2f 100644
> --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> @@ -25,6 +25,9 @@
>  /* Test if priv level is M or S. */
>  #define REQUIRE_PRIV_MS(ctx) do {          \
>      if (ctx->priv == PRV_U) {              \
> +        if (ctx->virt_enabled) {           \
> +            ctx->virt_inst_excp = true;    \
> +        }                                  \
>          return false;                      \
>      }                                      \
>  } while (0)
> diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> index f4e3051000..ea4b169422 100644
> --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx,
> arg_th_tst *a)
>  #define REQUIRE_PRIV_MSU(ctx)
>  
>  /* Test if priv level is M or S. */
> -#define REQUIRE_PRIV_MS(ctx)                                    \
> -do {                                                            \
> -    if (ctx->priv == PRV_U) {                                   \
> -        return false;                                           \
> -    }                                                           \
> +#define REQUIRE_PRIV_MS(ctx) do {          \
> +    if (ctx->priv == PRV_U) {              \
> +        if (ctx->virt_enabled) {           \
> +            ctx->virt_inst_excp = true;    \
> +        }                                  \
> +        return false;                      \
> +    }                                      \
>  } while (0)
>  
>  #define NOP_PRIVCHECK(insn, extcheck, privcheck)                \
Re: [PATCH v3] target/riscv/tcg: svinval instructions raise virtual instruction
Posted by Daniel Henrique Barboza 2 weeks ago 

On 9/11/2026 5:13 PM, Christian S. Lima wrote:
> The risc v privileged specification requires hinval.vvma, hinval.gvma,
> sfence.w.inval and sfence.inval.ir should raise a virtual instruction
> exception when executed in the vu-mode. This patch add the check to
> raise the virtual instruction exception when is in the vu-mode.
> 
> changes in v3:
> - Add missing semicolon
> 
> changes in v2:
> - Remove the wrong `return true;` from macro
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621
> 
> Signed-off-by: Christian S. Lima <christianslima@proton.me>

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

> ---
>   target/riscv/tcg/insn_trans/trans_svinval.c.inc |  3 +++
>   target/riscv/tcg/insn_trans/trans_xthead.c.inc  | 12 +++++++-----
>   2 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> index 4614c1489c..1341beba2f 100644
> --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> @@ -25,6 +25,9 @@
>   /* Test if priv level is M or S. */
>   #define REQUIRE_PRIV_MS(ctx) do {          \
>       if (ctx->priv == PRV_U) {              \
> +        if (ctx->virt_enabled) {           \
> +            ctx->virt_inst_excp = true;    \
> +        }                                  \
>           return false;                      \
>       }                                      \
>   } while (0)
> diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> index f4e3051000..ea4b169422 100644
> --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
>   #define REQUIRE_PRIV_MSU(ctx)
>   
>   /* Test if priv level is M or S. */
> -#define REQUIRE_PRIV_MS(ctx)                                    \
> -do {                                                            \
> -    if (ctx->priv == PRV_U) {                                   \
> -        return false;                                           \
> -    }                                                           \
> +#define REQUIRE_PRIV_MS(ctx) do {          \
> +    if (ctx->priv == PRV_U) {              \
> +        if (ctx->virt_enabled) {           \
> +            ctx->virt_inst_excp = true;    \
> +        }                                  \
> +        return false;                      \
> +    }                                      \
>   } while (0)
>   
>   #define NOP_PRIVCHECK(insn, extcheck, privcheck)                \

Patchew 2.1-devel-ea86937

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