This series adds support for version 0.9 of the draft RISC-V Zvabd
extension. The extension provides vector integer absolute-difference
instructions for image, video, and other data-processing workloads.
It introduces eight new instructions:

  - vabd.vv, vabd.vx, vabdu.vv, and vabdu.vx support SEW values from
    8 through ELEN, with SEW 64 requiring Zve64x.
  - vwabda.vv, vwabda.vx, vwabdau.vv, and vwabdau.vx support SEW 8
    and 16 and accumulate into a double-width destination.

The specification is currently under review at:
https://github.com/riscv/riscv-isa-manual/pull/3279

The series implement this instruction extension, including instruction
decoder, TCG translation, helpers, and tests, etc.

Changes in v1:
  - Added support for recognizing the vabs.v pseudo-instruction in the disassembler.
  - Added tests for the eight Zvabd instructions based on Daniel's tests.

Changes in v2:
  - Order the switch cases numerically in patch 1.
  - Use .insn instead of .word to encode instructions in patch 3.
  - Refine the commit messages for patches 1 and 3.

Mingliang Liu (2):
  disas/riscv: Support vabs.v pseudo-instruction
  tests/tcg/riscv64: Add Zvabd extension tests

Zhibo Hong (1):
  target/riscv: Add support for the Zvabd extension

 disas/riscv-op.c.inc                        |   9 +
 disas/riscv.c                               |  14 +
 target/riscv/cpu.c                          |   1 +
 target/riscv/cpu_cfg_fields.h.inc           |   1 +
 target/riscv/helper.h                       |  26 +
 target/riscv/insn32.decode                  |  10 +
 target/riscv/tcg/insn_trans/trans_rvv.c.inc |  45 ++
 target/riscv/tcg/tcg-cpu.c                  |   6 +
 target/riscv/tcg/vector_helper.c            |  56 ++
 tests/tcg/riscv64/Makefile.softmmu-target   |   8 +
 tests/tcg/riscv64/test-zvabd.S              | 659 ++++++++++++++++++++
 11 files changed, 835 insertions(+)
 create mode 100644 tests/tcg/riscv64/test-zvabd.S

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2.39.5