[v1] hex queue | Patchew

[PULL 0/9] hex queue

Brian Cain posted 9 patches 2 weeks, 6 days ago

Diff against v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v2 v2 v3 v4 v5
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260905200550.2009799-1-brian.cain@oss.qualcomm.com

Maintainers: Brian Cain <brian.cain@oss.qualcomm.com>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

There is a newer version of this series

target/hexagon/gen_tcg.h                    | 28 ++++++++++++++++++++++++++++
hw/hexagon/hexagon_dsp.c                    | 23 +++++++++++++++++++++++
hw/hexagon/hexagon_tlb.c                    | 10 ++++++++++
hw/intc/hex-l2vic.c                         | 13 +++++++++----
target/hexagon/genptr.c                     |  1 +
target/hexagon/hex_interrupts.c             |  2 +-
target/hexagon/hex_mmu.c                    | 12 +++++++++---
target/hexagon/hexswi.c                     |  1 +
target/hexagon/op_helper.c                  |  9 +++++++++
target/hexagon/translate.c                  | 22 ++++++++--------------
target/hexagon/tag_rev_info.c.inc           | 10 ++++++++++
target/hexagon/imported/encode_pp.def       | 11 +++++++++++
target/hexagon/imported/system.idef         | 11 +++++++++++
tests/functional/hexagon/test_arch_tests.py |  6 +++---
tests/functional/hexagon/test_systests.py   | 17 +++++++++++++----
15 files changed, 147 insertions(+), 29 deletions(-)

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[PULL 0/9] hex queue

Posted by Brian Cain 2 weeks, 6 days ago

The following changes since commit ff1d2d19d7e24893e2012d879f8e73077e17b9bd:

  Merge tag 'pull-11.1-check-tcg-meson-040926-2' of https://gitlab.com/stsquad/qemu into staging (2026-09-04 16:52:58 +0100)

are available in the Git repository at:

  https://github.com/qualcomm/qemu tags/pull-hex-20260905

for you to fetch changes up to dfad6f9ff1a4600893ef6b3c21382225e604535e:

  target/hexagon: decode the DMA insts as unimp (2026-09-05 12:04:01 -0700)

----------------------------------------------------------------
hexagon: TLB, badva fixes + DMA

Add fixes for TLB, badva behavior and an unimp placeholder for the
DMA instruction set.

----------------------------------------------------------------
Brian Cain (9):
      hw/hexagon: register the V68N_1024 machine
      target/hexagon: read BADVA as an alias of BADVA0/1
      target/hexagon: kick vCPU when re-asserting interrupts
      hw/intc: name the L2VIC edge trigger check
      target/hexagon: assert guest register pair alignment
      hexagon: raise imprecise exception for multi-TLB matches
      tests/functional/hexagon: add tests, update to v0.2.14
      tests/functional/hexagon: update arch tests to v0.2.14
      target/hexagon: decode the DMA insts as unimp

 target/hexagon/gen_tcg.h                    | 28 ++++++++++++++++++++++++++++
 hw/hexagon/hexagon_dsp.c                    | 23 +++++++++++++++++++++++
 hw/hexagon/hexagon_tlb.c                    | 10 ++++++++++
 hw/intc/hex-l2vic.c                         | 13 +++++++++----
 target/hexagon/genptr.c                     |  1 +
 target/hexagon/hex_interrupts.c             |  2 +-
 target/hexagon/hex_mmu.c                    | 12 +++++++++---
 target/hexagon/hexswi.c                     |  1 +
 target/hexagon/op_helper.c                  |  9 +++++++++
 target/hexagon/translate.c                  | 22 ++++++++--------------
 target/hexagon/tag_rev_info.c.inc           | 10 ++++++++++
 target/hexagon/imported/encode_pp.def       | 11 +++++++++++
 target/hexagon/imported/system.idef         | 11 +++++++++++
 tests/functional/hexagon/test_arch_tests.py |  6 +++---
 tests/functional/hexagon/test_systests.py   | 17 +++++++++++++----
 15 files changed, 147 insertions(+), 29 deletions(-)

Re: [PULL 0/9] hex queue

Posted by Peter Maydell 2 weeks, 5 days ago

On Sat, 5 Sept 2026 at 21:05, Brian Cain <brian.cain@oss.qualcomm.com> wrote:
>
> The following changes since commit ff1d2d19d7e24893e2012d879f8e73077e17b9bd:
>
>   Merge tag 'pull-11.1-check-tcg-meson-040926-2' of https://gitlab.com/stsquad/qemu into staging (2026-09-04 16:52:58 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/qualcomm/qemu tags/pull-hex-20260905
>
> for you to fetch changes up to dfad6f9ff1a4600893ef6b3c21382225e604535e:
>
>   target/hexagon: decode the DMA insts as unimp (2026-09-05 12:04:01 -0700)
>
> ----------------------------------------------------------------
> hexagon: TLB, badva fixes + DMA
>
> Add fixes for TLB, badva behavior and an unimp placeholder for the
> DMA instruction set.
>
> ----------------------------------------------------------------
> Brian Cain (9):
>       hw/hexagon: register the V68N_1024 machine
>       target/hexagon: read BADVA as an alias of BADVA0/1
>       target/hexagon: kick vCPU when re-asserting interrupts
>       hw/intc: name the L2VIC edge trigger check
>       target/hexagon: assert guest register pair alignment
>       hexagon: raise imprecise exception for multi-TLB matches
>       tests/functional/hexagon: add tests, update to v0.2.14
>       tests/functional/hexagon: update arch tests to v0.2.14
>       target/hexagon: decode the DMA insts as unimp



Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/11.2
for any user-visible changes.

-- PMM