Additional test suites uncover some subtle issues with TLBs, interrupts
and badva register.
Brian Cain (8):
hw/hexagon: register the V68N_1024 machine
target/hexagon: read BADVA as an alias of BADVA0/1
target/hexagon: kick vCPU when re-asserting interrupts
hw/intc: name the L2VIC edge trigger check
target/hexagon: assert guest register pair alignment
hexagon: raise imprecise exception for multi-TLB matches
tests/functional/hexagon: add tests, update to v0.2.14
tests/functional/hexagon: update arch tests to v0.2.14
hw/hexagon/hexagon_dsp.c | 23 +++++++++++++++++++++
hw/hexagon/hexagon_tlb.c | 10 +++++++++
hw/intc/hex-l2vic.c | 13 ++++++++----
target/hexagon/hex_interrupts.c | 2 +-
target/hexagon/hex_mmu.c | 12 ++++++++---
target/hexagon/hexswi.c | 1 +
target/hexagon/op_helper.c | 9 ++++++++
target/hexagon/translate.c | 22 +++++++-------------
tests/functional/hexagon/test_arch_tests.py | 6 +++---
tests/functional/hexagon/test_systests.py | 17 +++++++++++----
10 files changed, 86 insertions(+), 29 deletions(-)
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2.34.1