The following changes since commit eb710c255642cd7dc947f25c9a06c9fc8191e98d:

  Merge tag 'firmware-20260901-pull-request' of https://gitlab.com/kraxel/qemu into staging (2026-09-01 10:38:45 +0100)

are available in the Git repository at:

  https://github.com/qualcomm/qemu tags/pull-hex-20260901

for you to fetch changes up to 4a4ba15b2b0de009c662674dd365ff56048e2b22:

  hw/hexagon: decode an empty TLB size field as 4KB (2026-09-01 18:23:23 -0700)

----------------------------------------------------------------
This PR adds semihosting, and fixes for exceptions, icinva, TLB, htid

----------------------------------------------------------------
Brian Cain (18):
      semihosting: add APIs for chardev-aware guest fd routing
      target/hexagon: Add an errno mapping
      python/machine: support routing semihosting output to the test console
      tests/functional: Add hexagon semihosting systests
      target/hexagon: align exceptions for user/sysemu
      tests/tcg/hexagon: check priv instructions raise SIGILL
      target/hexagon: guard writes to unimplemented guest registers
      target/hexagon: take BQL when reading the system pcycle count
      target/hexagon: gate GPCYCLE guest register reads on SSR:CE
      target/hexagon: read UTIMERLO/UTIMERHI from the global timer
      target/hexagon: raise imprecise exception on multi-TLB match
      target/hexagon: implement direct-to-guest interrupt delivery
      target/hexagon: fix iassign{r, w} to cover all threads
      tests/functional/hexagon: update to v0.2.12, +test_{interrupts, sys_regs}
      target/hexagon: invalidate translated code for user icinva
      tests/tcg/hexagon: add icinva test
      hw/hexagon: assign a distinct htid to each DSP machine CPU
      hw/hexagon: decode an empty TLB size field as 4KB

Matheus Tavares Bernardino (9):
      disas/hexagon: honour target byte order when printing instructions
      target/hexagon: fix store-conditional on big-endian hosts
      target/hexagon: fix PC advancement for non-COF TB terminators
      target/hexagon: add aux functions for guest mem load/store
      semihosting: add callback to set error
      target/hexagon: add semihosting support
      semihosting: add ftruncate helper (to be used for hexagon)
      target/hexagon: add main arch-specific semihosting operations
      target/hexagon: add COREDUMP semihosting operation

Sid Manning (1):
      hw/intc: clear pending bit on l2vic de-assertion

 docs/system/target-hexagon.rst              |   8 +-
 configs/targets/hexagon-softmmu.mak         |   2 +
 include/hw/hexagon/hexagon_tlb.h            |   3 +-
 include/semihosting/common-semi.h           |   2 +
 include/semihosting/console.h               |   9 +
 include/semihosting/guestfd.h               |   9 +
 include/semihosting/syscalls.h              |   2 +
 target/hexagon/cpu.h                        |   1 +
 target/hexagon/cpu_helper.h                 |   6 +
 target/hexagon/gen_tcg.h                    |   9 +
 target/hexagon/helper.h                     |   5 +
 target/hexagon/internal.h                   |   1 +
 target/hexagon/translate.h                  |   6 +-
 target/hexagon/reg_fields_def.h.inc         |   7 +
 disas/hexagon.c                             |   6 +-
 hw/hexagon/hexagon_dsp.c                    |   4 +
 hw/hexagon/hexagon_tlb.c                    |  29 +-
 hw/intc/hex-l2vic.c                         |   2 +
 linux-user/hexagon/cpu_loop.c               |  30 +-
 semihosting/arm-compat-semi.c               |   3 +-
 semihosting/console.c                       |   5 +
 semihosting/guestfd.c                       |   8 +
 semihosting/syscalls.c                      |  29 ++
 target/arm/common-semi-target.c             |   4 +
 target/hexagon/common-semi-target.c         |  51 ++
 target/hexagon/cpu.c                        |  17 +-
 target/hexagon/cpu_helper.c                 | 112 ++++-
 target/hexagon/genptr.c                     |  33 +-
 target/hexagon/hex_interrupts.c             |  91 +++-
 target/hexagon/hex_mmu.c                    |   5 +-
 target/hexagon/hexswi.c                     | 734 +++++++++++++++++++++++++++-
 target/hexagon/machine.c                    |   5 +-
 target/hexagon/op_helper.c                  |  85 ++--
 target/hexagon/translate.c                  |  72 ++-
 target/riscv/common-semi-target.c           |   4 +
 tests/tcg/hexagon/icinva.c                  |  70 +++
 tests/tcg/hexagon/privileged-insn.c         |  79 +++
 tests/tcg/hexagon/reg_mut.c                 |  11 +-
 hw/hexagon/Kconfig                          |   1 +
 python/qemu/machine/machine.py              |  10 +-
 qemu-options.hx                             |   8 +-
 target/hexagon/hex_common.py                |  18 +-
 target/hexagon/meson.build                  |   1 +
 tests/functional/hexagon/meson.build        |   5 +
 tests/functional/hexagon/test_arch_tests.py |  12 +-
 tests/functional/hexagon/test_systests.py   |  94 ++++
 tests/tcg/hexagon/Makefile.target           |   3 +
 47 files changed, 1573 insertions(+), 138 deletions(-)
 create mode 100644 target/hexagon/common-semi-target.c
 create mode 100644 tests/tcg/hexagon/icinva.c
 create mode 100644 tests/tcg/hexagon/privileged-insn.c
 create mode 100755 tests/functional/hexagon/test_systests.py

On Wed, 2 Sept 2026 at 05:43, Brian Cain <brian.cain@oss.qualcomm.com> wrote:
>
> The following changes since commit eb710c255642cd7dc947f25c9a06c9fc8191e98d:
>
>   Merge tag 'firmware-20260901-pull-request' of https://gitlab.com/kraxel/qemu into staging (2026-09-01 10:38:45 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/qualcomm/qemu tags/pull-hex-20260901
>
> for you to fetch changes up to 4a4ba15b2b0de009c662674dd365ff56048e2b22:
>
>   hw/hexagon: decode an empty TLB size field as 4KB (2026-09-01 18:23:23 -0700)
>
> ----------------------------------------------------------------
> This PR adds semihosting, and fixes for exceptions, icinva, TLB, htid
>



Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/11.2
for any user-visible changes.

-- PMM