[PATCH v4 0/3] hw/riscv: Add K230 DWC SSI Standard PIO support

Kangjie Huang posted 3 patches 3 weeks, 5 days ago
Maintainers: Chao Liu <chao.liu@processmission.com>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Paolo Bonzini <pbonzini@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>
MAINTAINERS                     |    2 +
docs/system/riscv/k230.rst      |    2 +
hw/riscv/Kconfig                |    2 +
hw/riscv/k230.c                 |  165 +++++-
hw/ssi/Kconfig                  |    5 +
hw/ssi/dwc_ssi.c                | 1108 +++++++++++++++++++++++++++++++++++++++
hw/ssi/meson.build              |    1 +
include/hw/riscv/k230.h         |    7 +
include/hw/ssi/dwc_ssi.h        |   80 +++
tests/qtest/k230-dwc-ssi-test.c |  720 +++++++++++++++++++++++++
tests/qtest/meson.build         |    3 +-
11 files changed, 2085 insertions(+), 10 deletions(-)
[PATCH v4 0/3] hw/riscv: Add K230 DWC SSI Standard PIO support
Posted by Kangjie Huang 3 weeks, 5 days ago
Hi,

This series adds a reusable Standard PIO model for the Synopsys DWC SSI
controller. The K230 machine has three of these controllers; the later
patches wire them into the machine.

The first patch implements the Standard SPI register subset, configurable
cs and FIFOs, the four Standard PIO transfer modes, interrupts,
reset and migration, and RAZ/WI for the unsupported enhanced SPI, DMA and
XIP registers. The model follows the DWC CTRLR0 layout where TMOD is at
bits [11:10]; the DW APB SSI variant (TMOD at bits [9:8]) is not
supported. The second patch instantiates the three K230 DWC SSI
controllers and connects their nine interrupt outputs to the PLIC. The
third patch attaches a standard SPI NOR flash to spi0 cs 0.

Changes since v3:

* Squashed the patches: interrupt support into the model patch, PLIC
  routing into the instantiation patch, so each patch has one clear job.
* Added the REGISTER Kconfig dependency for DWC_SSI.
* Listed the DWC SSI files explicitly in MAINTAINERS.
* Made the MWCR MHS bit writable so guest writes are no longer silently
  dropped, with a matching qtest.
* Added DWC_SSI_PHASE_COUNT; the migration check now uses >= COUNT.
* Replaced imr-reset with the master-mode property, which derives the IMR
  reset value per instance; serial-slave is not modelled.
* Removed the redundant SPI_FRF clearing and added an unimplemented warning.
* Documented  the frame-width constraint: the m25p80 family is an 8-bit
  byte-protocol device and needs DFS=7 (the reset default selects an
  8-bit frame); frames wider than 8 bits are logged with a warning.
* TX-only now drains the FIFO synchronously on DR writes: no more 64-frame
  batching, no more reads of TXFLR/SR to make progress, and no asymmetry
  with the TR path.

Enhanced SPI, internal IDMA, HI_SYS and XIP remain separate follow-up
series. The DW APB SSI TMOD encoding is outside the scope of this series.

Testing:

* Built qemu-system-riscv64 and the K230 DWC SSI qtest target.
* Ran the K230 DWC SSI qtests, covering all Standard PIO modes, register
  contracts, interrupt and PLIC routing, TX-only synchronous draining and
  standard SPI NOR reads.
* checkpatch.pl: 0 errors, 0 warnings.
* U-Boot read/write against the attached flash via sf probe/read/write.
* U-Boot loaded Linux from SPI flash and booted it to the command line.
* Linux spi-mem polling-path read/write with the vendor driver.
* Linux spi-mem reads, and writes whose total frame count does not exceed
  the FIFO depth.

Note: 
	a spi-mem write larger than the FIFO depth fails with
"CS de-assertion on Tx" (-EIO) in the K230 SDK driver's native-CS path.
The model sends the whole FIFO at once when SER is enabled, so the
driver's refill loop sees TXFLR=0 and mistakes that for a dropped CS. In
this model, an empty FIFO simply means the transfer is done.
https://github.com/kendryte/k230_sdk/blob/v2.0/src/little/linux/drivers/spi/spi-dw-core-k230.c#L733-L742

References:

K230 Technical Reference Manual:

https://github.com/revyos/external-docs/blob/79b3a79072412ead81427e6755b4d9e6d9ded8d8/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf

Linux DWC SSI driver and binding:

https://github.com/torvalds/linux/blob/f9a2394a23482bfd330911e9c8295b71724feacd/drivers/spi/spi-dw-core.c
https://github.com/torvalds/linux/blob/f9a2394a23482bfd330911e9c8295b71724feacd/drivers/spi/spi-dw.h
https://github.com/torvalds/linux/blob/f9a2394a23482bfd330911e9c8295b71724feacd/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml

This series supersedes the previous v3 series:

https://lore.kernel.org/qemu-devel/20260808182956.290561-1-flamboyant.h.01@gmail.com/T/

Signed-off-by: Kangjie Huang <flamboyant.h.01@gmail.com>
---
Kangjie Huang (3):
      hw/ssi: Add Synopsys DWC SSI standard PIO controller
      hw/riscv/k230: Instantiate DWC SSI controllers and route IRQs to PLIC
      hw/riscv/k230: Attach a standard SPI NOR flash

 MAINTAINERS                     |    2 +
 docs/system/riscv/k230.rst      |    2 +
 hw/riscv/Kconfig                |    2 +
 hw/riscv/k230.c                 |  165 +++++-
 hw/ssi/Kconfig                  |    5 +
 hw/ssi/dwc_ssi.c                | 1108 +++++++++++++++++++++++++++++++++++++++
 hw/ssi/meson.build              |    1 +
 include/hw/riscv/k230.h         |    7 +
 include/hw/ssi/dwc_ssi.h        |   80 +++
 tests/qtest/k230-dwc-ssi-test.c |  720 +++++++++++++++++++++++++
 tests/qtest/meson.build         |    3 +-
 11 files changed, 2085 insertions(+), 10 deletions(-)
---
base-commit: 562bae590f194fb590beb5c65da44fc35ab9f64a
change-id: 20260831-t_v4_spi_patch-d674c144222e

Best regards,
-- 
Kangjie Huang <flamboyant.h.01@gmail.com>