Based-on: 20260827041557.775080-1-richard.henderson@linaro.org
("[PATCH v4 0/6] target/arm: Introduce cpu types max-v8 and max-v9")
Another trivial little extension.
Like PSTATE.IL, the priority of the exception raised by PSTATE.UINJ
is below translation and below single-step. Thus we must defer to
translation, after such things have been recognized.
r~
Richard Henderson (13):
target/arm: Rename and adjust aarch32_max_v8_tcg_initfn
target/arm: Introduce cpu types max-v8 and max-v9
target/arm: Use -cpu max-v8 with aarch64=off
target/arm: Separate cpu types max-v8 and max-v9
target/arm: Move ID_AA64PFR2 feature tests together
target/arm: Add isar_feature_aa64_uinj
target/arm: Drop U from most PSTATE bits
target/arm: Clear PSTATE.UINJ when taking exceptions
target/arm: Widen cpsr_{read,write}_for_spsr_elx to uint64_t
target/arm: Read and write PSTATE.UINJ
target/arm: Add PSTATE.UINJ to tbflags
target/arm: Honor PSTATE.UINJ during translation
target/arm: Enable FEAT_UINJ for -cpu max-v9
target/arm/cpu-features.h | 26 +--
target/arm/cpu.h | 42 ++---
target/arm/internals.h | 11 +-
target/arm/tcg/translate.h | 2 +
hw/arm/sbsa-ref.c | 2 +
hw/arm/virt.c | 2 +
target/arm/cpu-max.c | 4 +-
target/arm/helper.c | 28 ++-
target/arm/tcg/cpu32.c | 8 +-
target/arm/tcg/cpu64.c | 161 ++++++++++++------
target/arm/tcg/helper-a64.c | 2 +
target/arm/tcg/hflags.c | 6 +
target/arm/tcg/stubs32.c | 2 +-
target/arm/tcg/translate-a64.c | 9 +
target/arm/tcg/translate.c | 17 ++
tests/qtest/arm-cpu-features.c | 4 +-
docs/system/arm/emulation.rst | 14 +-
.../aarch64/test_virt_aarch64_off.py | 4 +-
18 files changed, 243 insertions(+), 101 deletions(-)
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2.53.0