target/riscv: correct cbo and lq disassembly

[PATCH v3 0/1] target/riscv: correct cbo and lq disassembly

frederic.petrot@univ-grenoble-alpes.fr posted 1 patch 1 month ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260825100922.387919-1-frederic.petrot@univ-grenoble-alpes.fr

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Weiwei Li <liwei1518@gmail.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>

disas/riscv.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)

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[PATCH v3 0/1] target/riscv: correct cbo and lq disassembly

Posted by frederic.petrot@univ-grenoble-alpes.fr 1 month ago

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

The CBO instructions were, AFAIU, disassembled erroneously.
In addition, lq (load-quad, a RV128 instruction) shares the same
opcode space as the CBOs, which also led to incorrect dasm for that
instruction (understandable since RV128 is an experimental feature).
To avoid overlaps, we now require that lq is decoded only if
rd is not 0, as CBO requires the field corresponding to rd to be zero,
both in dasm and decodetree.

Changes in v3:
- rebase on master
- squash the 3 original patches, at they did not make sense
  anymore after rebasing

Frédéric Pétrot (1):
  disas/riscv.c: Correct dasm for cbo and lq

 disas/riscv.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

-- 
2.43.0

Re: [PATCH v3 0/1] target/riscv: correct cbo and lq disassembly

Posted by Alistair Francis 1 month ago

On Tue, 2026-08-25 at 12:09 +0200,
frederic.petrot@univ-grenoble-alpes.fr wrote:
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> 
> The CBO instructions were, AFAIU, disassembled erroneously.
> In addition, lq (load-quad, a RV128 instruction) shares the same
> opcode space as the CBOs, which also led to incorrect dasm for that
> instruction (understandable since RV128 is an experimental feature).
> To avoid overlaps, we now require that lq is decoded only if
> rd is not 0, as CBO requires the field corresponding to rd to be
> zero,
> both in dasm and decodetree.
> 
> Changes in v3:
> - rebase on master
> - squash the 3 original patches, at they did not make sense
>   anymore after rebasing
> 
> Frédéric Pétrot (1):
>   disas/riscv.c: Correct dasm for cbo and lq

Thanks!

Applied to riscv-to-apply.next

Alistair

> 
>  disas/riscv.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)