Hi,

This is a minimal v2 of the STM32F1xx Rust GPIO series. 

The generic device implements the STM32F1 CRL/CRH configuration layout,
IDR/ODR and atomic BSRR/BRR updates. The register behavior is based on the
STM32F100xx RM0041 reference manual. This revision also restricts MMIO to
aligned 32-bit accesses and corrects analog-input, released open-drain,
alternate-function fallback and reset-output behavior.

The SoC patch instantiates GPIOA through GPIOE only. The address table has an
explicit STM32F100_NUM_GPIOS size. If the Rust type is unavailable, the same
five address windows retain their existing unimplemented-device fallback
instead of being left unbacked.

This remains a basic GPIO model. LCKR configuration locking,
AFIO/peripheral routing, EXTI interrupts, precise Hi-Z resolution and RCC
clock gating are not implemented. LCKR writes are ignored and read as zero,
and GPIO pins are not connected directly to the NVIC because external
interrupts are routed through EXTI.

Here is the datasheet I refered: https://embedded.fel.cvut.cz/sites/default
/files/procesory/STM32/en.CD00246267___RM0041_STM32F100_Reference_Manual.pdf 
 Most hardware behavoir according to General-purpose and alternate-function I/Os
(GPIOs and AFIOs) chapter

All qtest pass,both for c and rust. Rust/no-Rust ARM build successfully, checkpath
pass with 4 MAINTAINERA wanings do not change intentionally. 

Changes since v1:
- rebased the series directly onto upstream QEMU rather than the repository's
  out-of-tree STM32F103 commit;
- moved SoC integration and QTests to upstream STM32F100RBT6;
- instantiated GPIOA-E instead of GPIOA-G;
- gave the GPIO address table an explicit size;
- retained GPIO UNIMP regions in builds without Rust;
- changed the hardware reference from RM0008 to RM0041;
- updated the crate integration for QEMU's current root Cargo workspace and
  cargo_ws Meson interface;
- enforced aligned 32-bit register accesses;
- corrected analog input, released open-drain sampling, AF fallback and
  reset output deassertion;
- made unsupported LCKR writes read back as zero instead of suggesting that
  locking succeeded;
- retargeted the existing QTests and native tests and added focused
  regression cases for these changes;

Thanks,
Jack Wang

Signed-off-by: Jack Wang <163wangjack@gmail.com>
---
Jack Wang (5):
      hw/gpio: add STM32F1xx GPIO device model in Rust
      rust: add hw/gpio crate to the workspace
      hw/arm/stm32f100: instantiate and map GPIO ports
      tests/qtest: add STM32F100 GPIO tests
      rust/hw/gpio: add native unit tests

 Cargo.lock                        |  15 ++
 Cargo.toml                        |   1 +
 hw/arm/Kconfig                    |   1 +
 hw/arm/stm32f100_soc.c            |  35 ++-
 hw/gpio/Kconfig                   |   5 +
 hw/gpio/trace-events              |   7 +
 include/hw/arm/stm32f100_soc.h    |   2 +
 rust/hw/Kconfig                   |   1 +
 rust/hw/gpio/Cargo.toml           |  30 +++
 rust/hw/gpio/Kconfig              |   4 +
 rust/hw/gpio/meson.build          |  49 ++++
 rust/hw/gpio/src/bindings.rs      |  19 ++
 rust/hw/gpio/src/gpio.rs          | 491 ++++++++++++++++++++++++++++++++++++++
 rust/hw/gpio/src/lib.rs           |   3 +
 rust/hw/gpio/tests/tests.rs       | 216 +++++++++++++++++
 rust/hw/meson.build               |   1 +
 tests/qtest/meson.build           |   4 +
 tests/qtest/stm32f100_gpio-test.c | 380 +++++++++++++++++++++++++++++
 18 files changed, 1259 insertions(+), 5 deletions(-)
---
base-commit: eea8fe61b8be8f3016e522e6af24924a0266ca95
change-id: 20260822-stm32f100-gpio-v2-final-69cc48d18429

Best regards,
--  
Jack Wang <163wangjack@gmail.com>