We just need to remove TARGET_AARCH64. Simply expose all the code and
conditionnally register types.
This fixes single-binary with arm + aarch64 targets.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/arm/tcg/cpu32.c     | 13 +++++++------
 target/arm/tcg/meson.build |  2 +-
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index bc07e33877a..c0fd8fb83da 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -18,10 +18,6 @@
 #endif
 #include "cpregs.h"
 
-
-/* CPU models. These are not needed for the AArch64 linux-user build. */
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-
 static void arm926_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -750,6 +746,13 @@ static void arm_tcg_cpu_register_types(void)
 {
     size_t i;
 
+    /* CPU models. These are not needed for the AArch64 linux-user build. */
+#ifdef CONFIG_USER_ONLY
+    if (target_aarch64()) {
+        return;
+    }
+#endif
+
     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
         arm_cpu_register(&arm_tcg_cpus[i]);
     }
@@ -757,8 +760,6 @@ static void arm_tcg_cpu_register_types(void)
 
 type_init(arm_tcg_cpu_register_types)
 
-#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
-
 /* Share AArch32 -cpu max features with AArch64. */
 void aa32_max_features(ARMCPU *cpu)
 {
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index cbfac0036e7..99dddfd45fd 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -30,7 +30,7 @@ translate32_d = [
 arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
 arm_stubs_ss.add(files('stubs32.c'))
 
-arm_ss.add(files(
+arm_common_user_system_ss.add(files(
   'cpu32.c',
 ))
 
-- 
2.43.0

On Fri, 21 Aug 2026 at 22:35, Pierrick Bouvier
<pierrick.bouvier@oss.qualcomm.com> wrote:
>
> We just need to remove TARGET_AARCH64. Simply expose all the code and
> conditionnally register types.
> This fixes single-binary with arm + aarch64 targets.
>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

RTH has proposed an alternative in
https://patchew.org/QEMU/20260827041557.775080-1-richard.henderson@linaro.org/20260827041557.775080-3-richard.henderson@linaro.org/
 -- are you OK with that approach instead, or do you prefer this patch?

thanks
-- PMM

On 8/27/2026 7:20 AM, Peter Maydell wrote:
> On Fri, 21 Aug 2026 at 22:35, Pierrick Bouvier
> <pierrick.bouvier@oss.qualcomm.com> wrote:
>>
>> We just need to remove TARGET_AARCH64. Simply expose all the code and
>> conditionnally register types.
>> This fixes single-binary with arm + aarch64 targets.
>>
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> 
> RTH has proposed an alternative in
> https://patchew.org/QEMU/20260827041557.775080-1-richard.henderson@linaro.org/20260827041557.775080-3-richard.henderson@linaro.org/
>  -- are you OK with that approach instead, or do you prefer this patch?
>

Yes it works for me!

> thanks
> -- PMM

Regards,
Pierrick

On 8/21/2026 2:35 PM, Pierrick Bouvier wrote:
> We just need to remove TARGET_AARCH64. Simply expose all the code and
> conditionnally register types.
> This fixes single-binary with arm + aarch64 targets.
> 
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
>  target/arm/tcg/cpu32.c     | 13 +++++++------
>  target/arm/tcg/meson.build |  2 +-
>  2 files changed, 8 insertions(+), 7 deletions(-)
> 

Ping for this simple patch.

Regards,
Pierrick