Fix alignment check for misa write

[PATCH v2 0/2] Fix alignment check for misa write

Vladimir Isaev posted 2 patches 1 month, 1 week ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260817150653.40357-1-vvisaev@gmail.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>

target/riscv/tcg/csr.c                    | 10 ++-
tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
tests/tcg/riscv64/test-misa-w.S           | 88 +++++++++++++++++++++++
3 files changed, 99 insertions(+), 3 deletions(-)
create mode 100644 tests/tcg/riscv64/test-misa-w.S

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[PATCH v2 0/2] Fix alignment check for misa write

Posted by Vladimir Isaev 1 month, 1 week ago

Current version disable misa.C on misa write when next instruciton is
not aligned, fix it and add test.

Changes from v1:
  - Use the test from https://lore.kernel.org/r/20260321144554.606417-2-npiggin@gmail.com,
    since it is much more comprehensive than mine.
  - Add GUEST_ERROR_LOG on a bad write attempt.

Vladimir Isaev (2):
  riscv: csr: do not drop C bit on misa write
  tests/tcg/riscv64: add misa write test

 target/riscv/tcg/csr.c                    | 10 ++-
 tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
 tests/tcg/riscv64/test-misa-w.S           | 88 +++++++++++++++++++++++
 3 files changed, 99 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-misa-w.S

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2.55.0